Design and Verification of Adaptive Cache Coherence Protocols ...

Figure 5.7 gives the M-engine rules, in which only the sources of suspended messages are
recorded. The transient memory state T[dir,dir1] means that the memory has sent purge
requests to cache sites dir and has received writeback messages from cache sites dir1. The
memory uses FlushAck messages to acknowledge all suspended writeback messages. It is worth
pointing out that, if the memory remembers which writeback has been used to update the
memory, it can acknowledge that writeback message via a WbAck message to allow the cache
to retain a clean copy.
5.4 Soundness Proof of the WP Protocol
In this section, we prove the soundness of WP by showing that CRF can simulate WP. We
de ne a mapping function from WP to CRF, and show thatany imperative rule of WP can be
simulated in CRF with respect to the mapping function. The soundness of WP follows from
the fact that all the WP rules can be derived from the imperative and directive rules of WP.
The soundness proof is given under the assumption that messages can be reordered arbitrar-
ily in incoming and outgoing queues. Obviously, the soundness property cannot be compromised
in the presence of speci c reordering restrictions such asFIFO message passing. We rst present
the invariants that will be used throughout the proof all the invariants are given in the context
of the imperative rules of WP.
5.4.1 Some Invariants of WP
Lemma 15 includes two invariants that describe the correspondence between memory states,
cache states and messages in transit. Invariant (1) means that the directory shows that an
address is cached in a cache site if and only if the address is cached in the Clean or Dirty
state in the cache, oraCache or WbAck message is in transit from the memory to the cache,
or a Purge or Wb message is in transit from the cache to the memory. Furthermore, a clean
cell always contains the same value as the memory cell. Invariant (2) describes the message in
transit when the cache state shows that a writeback operation is being performed. It ensures
that a WbAck or FlushAck message can always be processed when it is received.
Lemma 15 Given a WP term s,
(1) Cell(a,v,T[id j-,-]) 2 Mem(s) ,
Cell(a,v,Clean) 2 Cache id(s) _ Cell(a,-,Dirty) 2 Cache id(s) _
Msg(H,id ,Cache,a,v) 2 MoutCin id (s) _ Msg(H,id ,WbAck,a) 2 MoutCin id (s) _
Msg(id ,H,Purge,a) 2 MinCout id (s) _ Msg(id ,H,Wb,a,-) 2 MinCout id (s)
(2) Cell(a,v,WbPending) 2 Cache id(s) ,
Msg(id ,H,Wb,a,v) 2 MinCout id (s) _ Cell(a,-,T[-,(id ,v)j-]) 2 Mem(s) _
Msg(H,id ,WbAck,a) 2 MoutCin id (s) _ Msg(H,id ,FlushAck,a) 2 MoutCin id (s)
Lemma 16 implies that, if a Cache message is on its way to a cache, then the address is not
cached in the cache or a FlushAck message is on its way to the cache. This ensures that a
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