Design and Verification of Adaptive Cache Coherence Protocols ...

(Rule MM32). The memory can choose to acknowledge the last writeback with a WbAckw mes-
sage to allow the cache to retain a WP copy (Rule MM33).
The memory processes an incoming Downwb, Downmw or DownVmw message as follows:
When the memory receives a Downwb message, if the memory state shows that the cache
contains a WP copy for the address, the memory removes the cache identi er from the
corresponding directory (Rules MM21 and MM22). If the memory state shows that
the cache contains a Migratory copy for the address, the memory updates the memory
state to indicate that the address is no longer cached in any cache (Rules MM23, MM24
and MM25). This can happen because the memory can voluntarily send an upgrade
message to upgrade a cache cell from WP to Migratory, while the cache has downgraded
the cache cell from WP to Base. The downgrade operation has higher priority than the
upgrade operation.
When the memory receivesaDownmw message, it sets the memory state to indicate that
the cache contains a WP copy for the address (Rules MM26, MM27 and MM28).
When the memory receives a DownVmw message, it updates the memory value and sets the
memory state to indicate that the cache contains a WP copy for the address (Rules MM29,
MM30 and MM31).
In addition, the Tw[ , ] state can be converted to C[ ]. This is necessary to ensure that a
transient memory state will become a stable memory state eventually so that stalled cache
requests can be serviced.
Voluntary Rules There are ve voluntary rules that allow the memory to supply a cache
copy to a cache, to upgrade a cache cell or to downgrade a cache cell.
If the memory state is Cw[dir], the memory can send a Cachew message to supply a WP
copy to cache site id , where id =2 dir.
If the memory state is Cw[id ], the memory can send an Upwm message to cache site id
to upgrade the cache cell from WP to Migratory.
If the memory state is Cw[dir], the memory can multicast a DownReqwb message to cache
sites dir to downgrade the cache cells from WP to Base.
If the memory state is Cm[id ], the memory can send a DownReqmw message to cache site
id to downgrade the cache cell from Migratory to WP.
If the memory state is T 0 m[id ], the memory can send a DownReqwb message to cache site
id to downgrade the cache cell from WP to Base.
The memory state can be imprecise since it maintains no information about the existence
of Base cells. In addition, when the memory state shows that a cache contains a WP or
Migratory cell for an address, it is possible that the cache cell has already been downgraded.
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