Design and Verification of Adaptive Cache Coherence Protocols ...

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CRF-Storel-on-Invalid Rule Site(sache, ht,Storel(a,v)ipmb, mpb, proc) if a =2 sache ! Site(Cell(a,v,Dirty) j sache, pmb, mpbjht,Acki, proc) CRF-Commit-on-Dirty Rule Sys(mem, Site(Cell(a,v,Dirty) j sache, ht,Commit(a)ipmb, mpb, proc) j sites) ! Sys(mem[a:=v], Site(Cell(a,v,Clean) j sache, pmb, mpbjht,Acki, proc) j sites) CRF-Reconcile-on-Clean Rule Site(Cell(a,-,Clean) j sache, ht,Reconcile(a)ipmb, mpb, proc) ! Site(sache, pmb, mpbjht,Acki, proc) It is obvious that the stalled instruction rules given above can be derived from CRF rules: CRF-Loadl-on-Invalid = CRF-Cache + CRF-Loadl CRF-Storel-on-Invalid = CRF-Cache + CRF-Storel CRF-Commit-on-Dirty = CRF-Writeback + CRF-Commit CRF-Reconcile-on-Clean = CRF-Purge + CRF-Reconcile 3.2.2 Relaxed Execution Rules CRF gives precise conditions under which memory instructions can be reordered. In CRF, an instruction must be brought to the front of the processor-to-memory bu er before it can be executed. This constraint can be relaxed without a ecting program behaviors. For example, a Loadl instruction can be performed if there is no preceding Storel or Reconcile instruction to the same address. It is easy to derive the predicates under which a CRF instruction can be performed in the presence of other outstanding instructions: Loadl(a): no preceding Storel(a,-) or Reconcile(a) Storel(a,-): no preceding Loadl(a), Storel(a,-) or Fence w(-,a) Commit(a): no preceding Storel(a,-) Reconcile(a): no preceding Fence r(-,a) Fencer (a,-): no preceding Loadl(a) Fencew (a,-): no preceding Commit(a) The relaxed execution rules below allow a memory instruction to be performed before its preceding instructions are completed: CRF-Relaxed-Loadl Rule Site(sache, pmb1ht,Loadl(a)ipmb2, mpb, proc) if Cell(a,v,-) 2 sache ^ Storel(a,-), Reconcile(a) =2 pmb1 ! Site(sache, pmb1pmb2, mpbjht,vi, proc) CRF-Relaxed-Storel Rule Site(Cell(a,-,-) j sache, pmb1ht,Storel(a,v)ipmb2, mpb, proc) if Loadl(a), Storel(a,-), Fence w(-,a) =2 pmb1 ! Site(Cell(a,v,Dirty) j sache, pmb1pmb2, mpbjht,Acki, proc) 56
CRF-Relaxed-Commit Rule Site(sache, pmb1ht,Commit(a)ipmb2, mpb, proc) if Cell(a,-,Dirty) =2 sache ^ Store(a,-) =2 pmb1 ! Site(sache, pmb1pmb2, mpbjht,Acki, proc) CRF-Relaxed-Reconcile Rule Site(sache, pmb1ht,Reconcile(a)ipmb2, mpb, proc) if Cell(a,-,Clean) =2 sache ^ Fence r(-,a) =2 pmb1 ! Site(sache, pmb1pmb2, mpbjht,Acki, proc) CRF-Relaxed-Fencer Rule Site(sache, pmb1ht,Fencer (a,-)ipmb2, mpb, proc) if Loadl(a) =2 pmb1 ! Site(sache, pmb1pmb2, mpbjht,Acki, proc) CRF-Relaxed-Fence w Rule Site(sache, pmb1ht,Fencew (a,-)ipmb2, mpb, proc) if Commit(a) =2 pmb1 ! Site(sache, pmb1pmb2, mpbjht,Acki, proc) The relaxed execution rules imply that the processor can dispatch CRF instructions out- of-order without a ecting program behaviors in multiprocessor systems. For example, a Loadl instruction can be dispatched as long as there is no preceding Storel or Reconcile instruction to the same address which has not been dispatched. 3.3 Coarse-grain CRF Instructions In CRF, it is always safe to insert Commit, Reconcile and Fence instructions without a ecting the correctness of the program. This is because a dirty copy can always be written back to the memory, a clean copy can always be purged, and a sequential execution of instructions always produces a correct result. An extra Commit, Reconcile or Fence instruction may eliminate a legal program behavior but can never admit an illegal program behavior. This fact allows us to introduce coarse-grain versions of such instructions, which are more practical at the ISA level. A coarse-grain fence imposes an ordering constraint with respect to address ranges, instead of individual locations. For example, Fencerw(A1,A2) ensures that all preceding Loadl operations to address range A1 must be performed before any following Storel operation to address range A2 can be performed. It can be de ned in terms of jA1j jA2j ne-grain fences that obey all the reordering rules given earlier. Similarly, Commit(A) and Reconcile(A) can be de ned in terms of ne-grain commit and reconcile operations, respectively. An address range can be a cache line, a page or even the whole address space (we represent the address space by ` '). Of particular interest are memory fences that impose ordering constraints between some memory range and an individual location. For example, we can de ne the following coarse- grain fences: 57
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CSAIL Computer Science and Artifici
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Design and Veri cation of Adaptive
Page 8 and 9: I am truly grateful to my parents f
Page 10 and 11: 4 The Base Cache Coherence Protocol
Page 13 and 14: List of Figures 1.1 Impact of Archi
Page 15 and 16: Chapter 1 Introduction Shared memor
Page 17 and 18: transparent and exposed only for lo
Page 19 and 20: Example 1: Can both registers r1 an
Page 21 and 22: and release locks, which guard ever
Page 23 and 24: that are interconnected with an o -
Page 25 and 26: although various techniques have be
Page 27 and 28: y showing that each processor can a
Page 29 and 30: s1 if p (s1) ! s2 where s1 and s2 a
Page 31 and 32: Program counter (pc) +1 Instruction
Page 33 and 34: Branch target buffer (btb) Program
Page 35 and 36: instruction is waiting to be dispat
Page 37 and 38: Current State: Proc(ia, rf , rob, b
Page 39 and 40: Rule Name mem pmb mpb Next mem Next
Page 41 and 42: Specification Implementation t 1 B
Page 43 and 44: Intuitively, \2P " means that \P is
Page 45 and 46: (a) (b) PC 1005 PC 2000 Instruction
Page 47 and 48: ewritten to s2 according to rule R.
Page 49 and 50: It can be shown that the relaxed di
Page 51 and 52: Chapter 3 The Commit-Reconcile & Fe
Page 53 and 54: Producer Storel(a,v) Commit(a) Cons
Page 55 and 56: Commit/Reconcile Purge Loadl/Commit
Page 57: instructions, because of the lack o
Page 61 and 62: 3.4 Universality of the CRF Model M
Page 63 and 64: Translation from CRF to PSO: The Fe
Page 65 and 66: proc proc proc pmb mpb pmb mpb pmb
Page 67 and 68: Chapter 4 The Base Cache Coherence
Page 69 and 70: can be classi ed into two non-overl
Page 71 and 72: arbitrarily in an outgoing queue (t
Page 73 and 74: 4.3 The Imperative Rules of the Bas
Page 75 and 76: Imperative Processor Rules Instruct
Page 77 and 78: Figure 4.5 de nes the rules of the
Page 79 and 80: 4.5.2 Mapping from Base to CRF We d
Page 81 and 82: Base Imperative Rule CRF Rule IP1 (
Page 83 and 84: Base Rule Base Imperative Rule P1 I
Page 85 and 86: eceives a CacheReq message, it will
Page 87 and 88: e completed if it has an in nite nu
Page 89 and 90: SYS Sys(MSITE, SITEs) System MSITE
Page 91 and 92: Commit/Reconcile C-Receive-WbAck Ru
Page 93 and 94: message can be resumed eventually.
Page 95 and 96: If the memory state shows that the
Page 97 and 98: 5.3.3 FIFO Message Passing The live
Page 99 and 100: Figure 5.7 gives the M-engine rules
Page 101 and 102: Backward-Message-Cache-to-Mem-for-W
Page 103 and 104: 5.4.3 Simulation of WP in CRF Theor
Page 105 and 106: WP Imperative Rule CRF Rules IP1 (L
Page 107 and 108: WP Rule WP Imperative & Directive R
Page 109 and 110:
(4) Msg(H,id ,Cache,a,-)" 2 Cin id(
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This completes the proof according
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emains as CachePending, there mustb
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M-engine Rules Msg from id Mstate A
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Chapter 6 The Migratory Cache Coher
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Commit/Reconcile Send Purge Loadl/C
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Mandatory Processor Rules Instructi
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while the memory sends a FlushReq m
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Lemma 38 D is strongly terminating
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Migratory Imperative Rule CRF Rules
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Cell(a,v,C[id ]) 2 Mem(s) _ Cell(a,
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According to Theorem-C and Lemma 45
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CacheReq message. In the latter cas
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Chapter 7 Cachet: A Seamless Integr
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7.1.1 Putting Things Together It is
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Writeback Operations In Cachet, a w
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Composite Message Equivalent Sequen
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Imperative Processor Rules Instruct
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Invalid Commit/Reconcile Receive Ca
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Composite Imperative C-engine Rules
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7.4 The Cachet Cache Coherence Prot
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Voluntary C-engine Rules Cstate Act
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The memory processes an incoming Ca
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The inaccuracy of memory states can
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C-engine Rule of Cachet Deriving Im
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Composite Mandatory Processor Rules
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memory regions simultaneously. In a
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Chapter 8 Conclusions This thesis h
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and heuristic policies. Mandatory r
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technique can be used to allow a ca
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Voluntary C-engine Rules Cstate Act
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FIFO Message Passing msg1 msg2 msg2
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[13] J. K. Archibald. The Cache Coh
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[41] A. Erlichson, N. Nuckolls, G.
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[71] J. Kuskin, D. Ofelt, M. Heinri
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[101] F. Pong and M. Dubois. A New
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