Design and Verification of Adaptive Cache Coherence Protocols ...

DownReqmb: The memory requests a cache cell to downgrade from Migratory to Base.
The message behaves as DownReqmw followed by aDownReqwb.
In the remainder of this chapter, we rst design Cachet with only the basic messages. We
then de ne the complete Cachet protocol by incorporating composite operations that use com-
posite messages. The incorporation of composite operations can improve the performance of
the system but cannot compromise the soundness and liveness of the protocol. The notion of
composite messages and composite operations can remarkably simplify the design and veri ca-
tion of sophisticated cache coherence protocols such asCachet, since composite composite rules
do not have to be considered throughout the veri cation. It su ces to verify the correctness in
the presence of basic messages only.
7.3 The Imperative Rules of the Cachet Protocol
The imperative rules of Cachet contain three sets of rules, the processor rules, the cache engine
rules and the memory engine rules.
7.3.1 Imperative Processor Rules
Figure 7.5 gives the imperative processor rules of Cachet. It includes the imperative proces-
sor rules from the Base, WP and Migratory protocols. When an instruction is retired, it is
removed from the processor-to-memory bu er while an appropriate reply is provided via the
memory-to-processor bu er. The reply can be the requested data for a Loadl instruction, or
the corresponding acknowledgment for a Storel, Commit and Reconcile instruction.
A Loadl instruction can be completed if the address is cached in the Clean or Dirty state
of any protocol.
A Storel instruction can be completed if the address is cached in the Clean or Dirty state
of any protocol. The cache state is set to Dirty while the cache value is updated.
A Commit instruction can be completed if the addressed is uncached, or cached in the
Clean state of any protocol or the Dirty state of the Migratory protocol.
A Reconcile instruction can be completed if the address is uncached, or cached in the
Dirty state of any protocol or the Clean state of the WP or Migratory protocol.
7.3.2 Imperative Cache Engine Rules
Figure 7.6 gives the imperative C-engine rules of Cachet. When a cache engine processes an
incoming message, it immediately removes the message from the incoming queue.
Acache can purge a clean Base cell (Rule IC1).
A cache can write the dirty dataof a Base cell back to the memory via a Wbb message
and set the cache state to WbPending, indicating that a writeback operation is being
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