Design and Verification of Adaptive Cache Coherence Protocols ...

It can be shown that the relaxed dispatch rules have no semantic impact on program behav-
iors in multiprocessor systems that employ the relaxed memory access rules. This is obvious
because a processor dispatches a memory instruction only when there is no data dependence
between the instruction and all the preceding instructions which have not been dispatched.
The relaxed dispatch rules do not allow a memory instruction to be dispatched if a preceding
instruction contains an unresolved tag. A more aggressive implementation can relax this con-
straint so that a memory instruction can be dispatched even if a preceding instruction contains
an unknown address or data, as long as there is no data dependence. Furthermore, we can
allow speculative load instructions to be dispatched. (This requires slight modi cation of the
branch completion rules since a dispatched load instruction on a wrong speculation path cannot
be killed before the response from the memory is discarded). Therefore, a load instruction can
be dispatched if there is no undispatched store in front itintherob that may write to the same
address a store instruction can be dispatched if it is not on a speculative path and there is
no undispatched load or store in front it in the rob that may read from or write to the same
address.
Aggressive-Dispatch-Load Rule
Sys(Proc(ia, rf , rob1 Itb(ia1,t :=Load(a,U),Wr(r)) rob2, btb, im), pmb, mpb, mem)
if Store(a,-,U), Store(t 0 ,-,U) =2 rob1
! Sys(Proc(ia, rf , rob1 Itb(ia1,t :=Load(a,D),Wr(r)) rob2, btb, im), pmbht,Load(a)i, mpb,
Aggressive-Dispatch-Store Rule
Sys(Proc(ia, rf , rob1 Itb(ia1,t :=Store(a,v,U)) rob2, btb, im), pmb, mpb, mem)
mem)
if Jz, Load(a,U), Load(t 0 ,U), Store(a,-,U), Store(t 0 ,-,U) =2 rob1
! Sys(Proc(ia, rf , rob1 Itb(ia1,t :=Store(a,v,D)) rob2, btb, im), pmbht,Store(a,v)i, mpb, mem)
In the architectural optimizations we have discussed so far, we do not allow value specula-
tion [82, 83]. A memory instruction cannot be performed if it has an unknown address or data.
Furthermore, a load instruction cannot be performed if a preceding store instruction has an
unresolved address, and a store instruction cannot be performed if a preceding load or store
instruction has an unresolved address. We also do not allow speculative store instructions. Such
constraints can be relaxed with value speculation to achieve better performance. Conceptually,
value speculation allows a processor to chose an arbitrary value for any unresolved variable at
any time, provided that all the speculative instructions can be killed if the speculation turns
out to be wrong. Many speculative mechanisms and compiler optimizations are special cases
of value speculation. However, the impact of value speculation on program behaviors can be
di cult to understand in multiprocessor systems.
Modern microprocessors contain various architecture features designed to improve performance,
such as branch prediction, speculative execution, non-blocking caches, dynamic scheduling,
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