Design and Verification of Adaptive Cache Coherence Protocols ...

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Mandatory Processor Rules Instruction Cstate Action Next Cstate Loadl(a) Cell(a,v,Clean) retire Cell(a,v,Clean) P1 SF Cell(a,v,Dirty) retire Cell(a,v,Dirty) P2 SF Cell(a,v,WbPending) stall Cell(a,v,WbPending) P3 Cell(a,-,CachePending) stall Cell(a,-,CachePending) P4 a =2 cache stall Cell(a,-,CachePending) P5 hCacheReq,ai !H Storel(a,v) Cell(a,-,Clean) retire Cell(a,v,Dirty) P6 SF Cell(a,-,Dirty) retire Cell(a,v,Dirty) P7 SF Cell(a,v1,WbPending) stall Cell(a,v1,WbPending) P8 Cell(a,-,CachePending) stall Cell(a,-,CachePending) P9 a =2 cache stall Cell(a,-,CachePending) P10 hCacheReq,ai !H Commit(a) Cell(a,v,Clean) retire Cell(a,v,Clean) P11 SF Cell(a,v,Dirty) stall Cell(a,v,WbPending) P12 hWb,a,vi!H Cell(a,v,WbPending) stall Cell(a,v,WbPending) P13 Cell(a,-,CachePending) stall Cell(a,-,CachePending) P14 a =2 cache retire a =2 cache P15 SF Reconcile(a) Cell(a,v,Clean) retire Cell(a,v,Clean) P16 SF Cell(a,v,Dirty) retire Cell(a,v,Dirty) P17 SF Cell(a,v,WbPending) stall Cell(a,v,WbPending) P18 Cell(a,-,CachePending) stall Cell(a,-,CachePending) P19 a =2 cache retire a =2 cache P20 SF Voluntary C-engine Rules Cstate Action Next Cstate Cell(a,-,Clean) hPurge,ai!H a =2 cache VC1 Cell(a,v,Dirty) hWb,a,vi!H Cell(a,v,WbPending) VC2 a =2 cache hCacheReq,ai !H Cell(a,-,CachePending) VC3 Mandatory C-engine Rules Msg from H Cstate Action Next Cstate hCache,a,vi a =2 cache Cell(a,v,Clean) MC1 Cell(a,-,CachePending) Cell(a,v,Clean) MC2 hWbAck,ai Cell(a,v,WbPending) Cell(a,v,Clean) MC3 hFlushAck,ai Cell(a,-,WbPending) a =2 cache MC4 hPurgeReq,ai Cell(a,-,Clean) hPurge,ai!H a =2 cache MC5 Cell(a,v,Dirty) hWb,a,vi!H Cell(a,v,WbPending) MC6 Cell(a,v,WbPending) Cell(a,v,WbPending) MC7 Cell(a,-,CachePending) Cell(a,-,CachePending) MC8 a =2 cache a =2 cache MC9 Voluntary M-engine Rules Mstate Action Next Mstate Cell(a,v,C[dir]) (id =2 dir) hCache,a,vi!id Cell(a,v,C[id jdir]) VM1 Cell(a,v,C[dir]) (dir 6= ) hPurgeReq,ai!dir Cell(a,v,T[dir, ]) VM2 Mandatory M-engine Rules Msg from id Mstate Action Next Mstate hCacheReq,ai Cell(a,v,C[dir]) (id =2 dir) hCache,a,vi!id Cell(a,v,C[id jdir]) MM1 SF Cell(a,v,C[dir]) (id 2 dir) Cell(a,v,C[dir]) MM2 Cell(a,v,T[dir,sm]) (id =2 dir) stall message Cell(a,v,T[dir,sm]) MM3 Cell(a,v,T[dir,sm]) (id 2 dir) Cell(a,v,T[dir,sm]) MM4 hWb,a,vi Cell(a,v1,C[id jdir]) hPurgeReq,ai!dir Cell(a,v1,T[dir,(id ,v)]) MM5 Cell(a,v1,T[id jdir,sm]) Cell(a,v1,T[dir,(id ,v)jsm]) MM6 hPurge,ai Cell(a,v,C[id jdir]) Cell(a,v,C[dir]) MM7 Cell(a,v,T[id jdir,sm]) Cell(a,v,T[dir,sm]) MM8 Cell(a,-,T[ ,(id ,v)jsm]) hFlushAck,ai!id Cell(a,v,T[ ,sm]) MM9 Cell(a,-,T[ ,(id ,v)]) hWbAck,ai !id Cell(a,v,C[id ]) MM10 Cell(a,v,T[ , ]) Cell(a,v,C[ ]) MM11 Figure 5.5: The WP Protocol 92
If the memory state shows that the address is uncached in the cache, there are two possible cases. The cache request is stalled for later processing if the memory state is a transient state otherwise the memory sends a cache message to supply the data to the requesting cache. When a cache request is stalled, it is bu ered properly so that following messages in the incoming queue can still be processed. This can be modeled by allowing incoming messages to be reordered with each other under certain conditions. For the WP protocol, the minimal requirement of bu er management is that a stalled message cannot block any following message that has a di erent source or di erent address. This requirement can be described as follows: WP's bu er management: msg1 msg2 msg2 msg1 if (Cmd(msg1)=CacheReq _ Cmd(msg2)=CacheReq) ^ (Src(msg1) 6=Src(msg2) _ Addr(msg1) 6=Addr(msg2)) There can be several stalled requests regarding the same address from di erent cache sites. The strong fairness of Rule MM1 preventsacache request from being stalled forever while cache requests or writeback messages from other caches are serviced again and again. In practice, we can use a FIFO queue for bu ered messages to ensure such fairness. The role of the memory is more complicated for writeback operations, because the memory must ensure that other cache copies of the same address are coherent. This can be achieved by multicasting a purge request to all the caches recorded in the directory, except the one from which the writeback is received. The writeback acknowledgment is withheld until the memory has received acknowledgements for all the purge requests. The transient state T[dir,sm] is used for the bookkeeping purpose in the memory. In the transient state, dir represents the cache sites which have not yet acknowledged the purge requests, and sm contains the suspended writeback message that the memory has received but has not yet acknowledged (only the source and the data need to be recorded). Each time the memory receives a purge acknowledgment, the directory is updated accord- ingly. The suspended writeback message is resumed after the directory becomes empty, that is, all the purge requests have been acknowledged. The memory can then update the value of the memory cell and send a writeback acknowledgment (WbAck) or a ush acknowledgment (FlushAck) to the cache. If the cache receives a WbAck acknowledgment, it retains a clean copy otherwise it purges its copy. If the memory receives more than one writeback message, it records all the writeback messages in the transient state. The suspended messages are resumed when the directory becomes empty. The memory acknowledges each writeback message via a FlushAck message (it may chose to acknowledge the last writeback message via a WbAck message since the cache contains the same value as the memory). This ensures that all the stale copies of the address are purged from the caches. 93
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CSAIL Computer Science and Artifici
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Design and Veri cation of Adaptive
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I am truly grateful to my parents f
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4 The Base Cache Coherence Protocol
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List of Figures 1.1 Impact of Archi
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Chapter 1 Introduction Shared memor
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transparent and exposed only for lo
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Example 1: Can both registers r1 an
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and release locks, which guard ever
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that are interconnected with an o -
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although various techniques have be
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y showing that each processor can a
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s1 if p (s1) ! s2 where s1 and s2 a
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Program counter (pc) +1 Instruction
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Branch target buffer (btb) Program
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instruction is waiting to be dispat
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Current State: Proc(ia, rf , rob, b
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Rule Name mem pmb mpb Next mem Next
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Specification Implementation t 1 B
Page 43 and 44: Intuitively, \2P " means that \P is
Page 45 and 46: (a) (b) PC 1005 PC 2000 Instruction
Page 47 and 48: ewritten to s2 according to rule R.
Page 49 and 50: It can be shown that the relaxed di
Page 51 and 52: Chapter 3 The Commit-Reconcile & Fe
Page 53 and 54: Producer Storel(a,v) Commit(a) Cons
Page 55 and 56: Commit/Reconcile Purge Loadl/Commit
Page 57 and 58: instructions, because of the lack o
Page 59 and 60: CRF-Relaxed-Commit Rule Site(sache,
Page 61 and 62: 3.4 Universality of the CRF Model M
Page 63 and 64: Translation from CRF to PSO: The Fe
Page 65 and 66: proc proc proc pmb mpb pmb mpb pmb
Page 67 and 68: Chapter 4 The Base Cache Coherence
Page 69 and 70: can be classi ed into two non-overl
Page 71 and 72: arbitrarily in an outgoing queue (t
Page 73 and 74: 4.3 The Imperative Rules of the Bas
Page 75 and 76: Imperative Processor Rules Instruct
Page 77 and 78: Figure 4.5 de nes the rules of the
Page 79 and 80: 4.5.2 Mapping from Base to CRF We d
Page 81 and 82: Base Imperative Rule CRF Rule IP1 (
Page 83 and 84: Base Rule Base Imperative Rule P1 I
Page 85 and 86: eceives a CacheReq message, it will
Page 87 and 88: e completed if it has an in nite nu
Page 89 and 90: SYS Sys(MSITE, SITEs) System MSITE
Page 91 and 92: Commit/Reconcile C-Receive-WbAck Ru
Page 93: message can be resumed eventually.
Page 97 and 98: 5.3.3 FIFO Message Passing The live
Page 99 and 100: Figure 5.7 gives the M-engine rules
Page 101 and 102: Backward-Message-Cache-to-Mem-for-W
Page 103 and 104: 5.4.3 Simulation of WP in CRF Theor
Page 105 and 106: WP Imperative Rule CRF Rules IP1 (L
Page 107 and 108: WP Rule WP Imperative & Directive R
Page 109 and 110: (4) Msg(H,id ,Cache,a,-)" 2 Cin id(
Page 111 and 112: This completes the proof according
Page 113 and 114: emains as CachePending, there mustb
Page 115 and 116: M-engine Rules Msg from id Mstate A
Page 117 and 118: Chapter 6 The Migratory Cache Coher
Page 119 and 120: Commit/Reconcile Send Purge Loadl/C
Page 121 and 122: Mandatory Processor Rules Instructi
Page 123 and 124: while the memory sends a FlushReq m
Page 125 and 126: Lemma 38 D is strongly terminating
Page 127 and 128: Migratory Imperative Rule CRF Rules
Page 129 and 130: Cell(a,v,C[id ]) 2 Mem(s) _ Cell(a,
Page 131 and 132: According to Theorem-C and Lemma 45
Page 133 and 134: CacheReq message. In the latter cas
Page 135 and 136: Chapter 7 Cachet: A Seamless Integr
Page 137 and 138: 7.1.1 Putting Things Together It is
Page 139 and 140: Writeback Operations In Cachet, a w
Page 141 and 142: Composite Message Equivalent Sequen
Page 143 and 144: Imperative Processor Rules Instruct
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Invalid Commit/Reconcile Receive Ca
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Composite Imperative C-engine Rules
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7.4 The Cachet Cache Coherence Prot
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Voluntary C-engine Rules Cstate Act
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The memory processes an incoming Ca
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The inaccuracy of memory states can
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C-engine Rule of Cachet Deriving Im
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Composite Mandatory Processor Rules
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memory regions simultaneously. In a
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Chapter 8 Conclusions This thesis h
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and heuristic policies. Mandatory r
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technique can be used to allow a ca
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Voluntary C-engine Rules Cstate Act
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FIFO Message Passing msg1 msg2 msg2
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[13] J. K. Archibald. The Cache Coh
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[41] A. Erlichson, N. Nuckolls, G.
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[71] J. Kuskin, D. Ofelt, M. Heinri
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[101] F. Pong and M. Dubois. A New
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