Design and Verification of Adaptive Cache Coherence Protocols ...

Translation from CRF to PSO: The Fencerr and Fencerw instructions are translated into
Nop's, since PSO implicitly preserves the load-load and load-store ordering. Both Fencewr
and Fenceww are translated into Membar.
Translation from CRF to RMO: Since RMO assumes no ordering between memory ac-
cesses unless explicit memory barriers are inserted, the translation scheme translates each
CRF fence into the corresponding RMO memory barrier.
Translation from CRF to IBM 370: Since IBM 370's model is slightly stricter than the
TSO model, the translation can avoid some memory barriers by taking advantage from
the fact that IBM 370 prohibits data short-circuiting from write-bu ers. This suggests
that a Fencewr with identical pre-address and post-address be translated into a Nop.
We can translate programs based on release consistency to CRF programs by de ning the
release and acquire operations using CRF instructions and synchronization instructions such
as Lock/Unlock. The synchronization instructions are provided for mutual exclusion, and have
no ordering implication on other instructions. In terms of reordering constraints, a Lock can
be treated as a Loadl followed by a Storel, and an Unlock can be treated as a Storel.
Release(s) Commit( ) PreFenceW(s) Unlock(s)
Acquire(s) Lock(s) PostFenceR(s) Reconcile( )
One can think of the translation scheme above as the de nition of one version of release
consistency. Obviously, memory accesses after a release can be performed before the semaphore
is released, because the release only imposes a pre-fence on preceding accesses. Similarly, mem-
ory accesses before an acquire do not have to be completed before the semaphore is acquired,
because the acquire only imposes a post-fence on following memory accesses. Furthermore,
modi ed data of a store before a release need to be written back to the memory at the release
point, but a data copy of the address in another cache does not have to be invalidated or up-
dated immediately. This is because the stale data copy, if any, will be reconciled at the next
acquire point.
3.5 The Generalized CRF Model
In CRF, the memory behaves as the rendezvous of saches. A writeback operation is atomic
with respect to all the sites: if a sache can retrieve some data from the memory, another sache
must be able to retrieve the same data from the memory at the same time. Therefore, if two
stores are observed by more than one processor, they are observed in the same order provided
that the loads used in the observation are executed in order.
As an example, the following program illustrates that non-atomic store operations can
generate surprising behaviors even when only one memory location is involved. Assume initially
location a has value 0. Processors A and B modify location a while processors C and D read
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