Design and Verification of Adaptive Cache Coherence Protocols ...

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Imperative Processor Rules Instruction Cstate Action Next Cstate Loadl(a) Cell(a,v,Clean) retire Cell(a,v,Clean) IP1 Cell(a,v,Dirty) retire Cell(a,v,Dirty) IP2 Storel(a,v) Cell(a,-,Clean) retire Cell(a,v,Dirty) IP3 Cell(a,-,Dirty) retire Cell(a,v,Dirty) IP4 Commit(a) Cell(a,v,Clean) retire Cell(a,v,Clean) IP5 a =2 cache retire a =2 cache IP6 Reconcile(a) Cell(a,v,Dirty) retire Cell(a,v,Dirty) IP7 Cell(a,v,Clean) retire Cell(a,v,Clean) IP8 a =2 cache retire a =2 cache IP9 Imperative C-engine Rules Msg from H Cstate Action Next Cstate Cell(a,-,Clean) hPurge,ai!H a =2 cache IC1 Cell(a,v,Dirty) hWb,a,vi!H Cell(a,v,WbPending) IC2 hWbAck,ai Cell(a,v,WbPending) Cell(a,v,Clean) IC3 hFlushAck,ai Cell(a,-,WbPending) a =2 cache IC4 hCache,a,vi a =2 cache Cell(a,v,Clean) IC5 Imperative M-engine Rules Msg from id Mstate Action Next Mstate Cell(a,v,T[dir, ]) (id =2 dir) hCache,a,vi !id Cell(a,v,T[id jdir, ]) IM1 hPurge,ai Cell(a,v,T[id jdir,sm]) Cell(a,v,T[dir,sm]) IM2 hWb,a,vi Cell(a,v1,T[id jdir,sm]) Cell(a,v1,T[dir,smj(id ,v)]) IM3 Cell(a,-,T[ ,(id ,v)jsm]) hFlushAck,ai!id Cell(a,v,T[ ,sm]) IM4 Cell(a,-,T[ ,(id ,v)]) hWbAck,ai !id Cell(a,v,T[id , ]) IM5 Figure 5.4: Imperative Rules of WP M-Send-WbAck Rule Msite(Cell(a,-,T[ ,(id ,v)]) j mem, in, out) ! Msite(Cell(a,v,T[id , ]) j mem, in, out Msg(H,id ,WbAck,a)) Note that when a writeback message is suspended, the imperative rules rely on an oracle to inform the caches to purge or write back their copies so that the suspended message can be eventually resumed. The Imperative-&-Directive design methodology allows us to separate the soundness and liveness concerns. Figure 5.4 summarizes the imperative rules of WP. When an instruction is retired, it is removed from the processor-to-memory bu er while an appropriate response is supplied to the corresponding memory-to-processor bu er. When a message is received,itisremoved from the incoming queue. 5.3 The WP Protocol The imperative rules de ne all the coherence actions that can a ect the soundness of the system they intentionally do not address the liveness issue. For example, when the memory receives a writeback message, it suspends the message in the memory state. A suspended message can be resumed when the directory shows that the address is no longer cached in any cache. However, the imperative rules do not specify how to bring the system to such a state that a suspended 90
message can be resumed eventually. To ensure liveness, the memory must send a purge request to the caches in which the address is cached to force the address to be purged. We introduce two directive messages, CacheReq and PurgeReq, for this purpose. A cache can send a CacheReq message to the memory to request for a data copy the memory can send a PurgeReq message to a cache to force a clean copy to be purged or a dirty copy to be written back. In addition, we maintain some information about outstanding directive messages by splitting certain imperative cache and memory states. The Invalid state in the imperative rules corresponds to Invalid and CachePending in the integrated protocol, where CachePending implies that a CacheReq message has been sent to the memory. The T[dir, ] state in the imperative rules corresponds to T[dir, ] and C[dir] in the integrated protocol, where T[dir, ] implies that a PurgeReq message has been multicast to cache sites dir. Figure 5.5 de nes the rules of the WP protocol. The tabular description can be easily translated into formal TRS rules (cases that are not speci ed represent illegal or unreachable states). The processor rules are all mandatory rules. The cache engine and memory engine rules are categorized into mandatory and voluntary rules. Each mandatory rule is weakly fair in that if it can be applied, it must be applied eventually or become impossible to apply at some time. A mandatory rule marked with `SF' means the rule requires strong fairness to ensure the liveness of the system. The notation `msg ! dir' means sending the message msg to the destinations represented by directory dir. A processor rule may retire or stall an instruction depending on the cache state of the address. When an instruction is retired, it is removed from the processor-to-memory bu er and the corresponding value or reply is sent to the memory-to-processor bu er. When an instruction is stalled, it remains in the processor-to-memory bu er for later processing. A stalled instruction does not necessarily block other instructions to be executed. An incoming message can be processed or stalled depending on the memory state of the address. When a message is processed, it is removed from the incoming queue. When a message is stalled, it remains in the incoming queue for later processing (only CacheReq messages can be stalled). A stalled message is bu ered properly to avoid blocking following messages. 5.3.1 Mandatory Rules The processor rules are similar to those in the Base protocol, except that a Reconcile instruction can complete even when the address is cached in the Clean state. On acache miss, the cache sends a cache request to the memory and sets the cache state to be CachePending until the requested data is received. On a Commit instruction, if the address is cached in the Dirty state, the cache writes the data back to the memory and sets the cache state to be WbPending until a writeback acknowledgment is received. An instruction remains stalled when it cannot be completed in the current cache state. When the memory receives a CacheReq message, it processes the message according to the memory state. If the address is already cached in the cache, the cache request is discarded. 91
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CSAIL Computer Science and Artifici
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Design and Veri cation of Adaptive
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I am truly grateful to my parents f
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4 The Base Cache Coherence Protocol
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List of Figures 1.1 Impact of Archi
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Chapter 1 Introduction Shared memor
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transparent and exposed only for lo
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Example 1: Can both registers r1 an
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and release locks, which guard ever
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that are interconnected with an o -
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although various techniques have be
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y showing that each processor can a
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s1 if p (s1) ! s2 where s1 and s2 a
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Program counter (pc) +1 Instruction
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Branch target buffer (btb) Program
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instruction is waiting to be dispat
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Current State: Proc(ia, rf , rob, b
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Rule Name mem pmb mpb Next mem Next
Page 41 and 42: Specification Implementation t 1 B
Page 43 and 44: Intuitively, \2P " means that \P is
Page 45 and 46: (a) (b) PC 1005 PC 2000 Instruction
Page 47 and 48: ewritten to s2 according to rule R.
Page 49 and 50: It can be shown that the relaxed di
Page 51 and 52: Chapter 3 The Commit-Reconcile & Fe
Page 53 and 54: Producer Storel(a,v) Commit(a) Cons
Page 55 and 56: Commit/Reconcile Purge Loadl/Commit
Page 57 and 58: instructions, because of the lack o
Page 59 and 60: CRF-Relaxed-Commit Rule Site(sache,
Page 61 and 62: 3.4 Universality of the CRF Model M
Page 63 and 64: Translation from CRF to PSO: The Fe
Page 65 and 66: proc proc proc pmb mpb pmb mpb pmb
Page 67 and 68: Chapter 4 The Base Cache Coherence
Page 69 and 70: can be classi ed into two non-overl
Page 71 and 72: arbitrarily in an outgoing queue (t
Page 73 and 74: 4.3 The Imperative Rules of the Bas
Page 75 and 76: Imperative Processor Rules Instruct
Page 77 and 78: Figure 4.5 de nes the rules of the
Page 79 and 80: 4.5.2 Mapping from Base to CRF We d
Page 81 and 82: Base Imperative Rule CRF Rule IP1 (
Page 83 and 84: Base Rule Base Imperative Rule P1 I
Page 85 and 86: eceives a CacheReq message, it will
Page 87 and 88: e completed if it has an in nite nu
Page 89 and 90: SYS Sys(MSITE, SITEs) System MSITE
Page 91: Commit/Reconcile C-Receive-WbAck Ru
Page 95 and 96: If the memory state shows that the
Page 97 and 98: 5.3.3 FIFO Message Passing The live
Page 99 and 100: Figure 5.7 gives the M-engine rules
Page 101 and 102: Backward-Message-Cache-to-Mem-for-W
Page 103 and 104: 5.4.3 Simulation of WP in CRF Theor
Page 105 and 106: WP Imperative Rule CRF Rules IP1 (L
Page 107 and 108: WP Rule WP Imperative & Directive R
Page 109 and 110: (4) Msg(H,id ,Cache,a,-)" 2 Cin id(
Page 111 and 112: This completes the proof according
Page 113 and 114: emains as CachePending, there mustb
Page 115 and 116: M-engine Rules Msg from id Mstate A
Page 117 and 118: Chapter 6 The Migratory Cache Coher
Page 119 and 120: Commit/Reconcile Send Purge Loadl/C
Page 121 and 122: Mandatory Processor Rules Instructi
Page 123 and 124: while the memory sends a FlushReq m
Page 125 and 126: Lemma 38 D is strongly terminating
Page 127 and 128: Migratory Imperative Rule CRF Rules
Page 129 and 130: Cell(a,v,C[id ]) 2 Mem(s) _ Cell(a,
Page 131 and 132: According to Theorem-C and Lemma 45
Page 133 and 134: CacheReq message. In the latter cas
Page 135 and 136: Chapter 7 Cachet: A Seamless Integr
Page 137 and 138: 7.1.1 Putting Things Together It is
Page 139 and 140: Writeback Operations In Cachet, a w
Page 141 and 142: Composite Message Equivalent Sequen
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Imperative Processor Rules Instruct
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Invalid Commit/Reconcile Receive Ca
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Composite Imperative C-engine Rules
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7.4 The Cachet Cache Coherence Prot
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Voluntary C-engine Rules Cstate Act
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The memory processes an incoming Ca
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The inaccuracy of memory states can
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C-engine Rule of Cachet Deriving Im
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Composite Mandatory Processor Rules
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memory regions simultaneously. In a
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Chapter 8 Conclusions This thesis h
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and heuristic policies. Mandatory r
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technique can be used to allow a ca
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Voluntary C-engine Rules Cstate Act
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FIFO Message Passing msg1 msg2 msg2
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[13] J. K. Archibald. The Cache Coh
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[41] A. Erlichson, N. Nuckolls, G.
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[71] J. Kuskin, D. Ofelt, M. Heinri
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[101] F. Pong and M. Dubois. A New
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