Design and Verification of Adaptive Cache Coherence Protocols ...

Processor Rules
Rule Name Instruction Cstate Action Next Cstate
CRF-Loadl Loadl(a) Cell(a,v,Clean) retire Cell(a,v,Clean)
Cell(a,v,Dirty) retire Cell(a,v,Dirty)
CRF-Storel Storel(a,v) Cell(a,-,Clean) retire Cell(a,v,Dirty)
Cell(a,-,Dirty) retire Cell(a,v,Dirty)
CRF-Commit Commit(a) Cell(a,v,Clean) retire Cell(a,v,Clean)
a =2 sache retire a =2 sache
CRF-Reconcile Reconcile(a) Cell(a,v,Dirty) retire Cell(a,v,Dirty)
a =2 sache retire a =2 sache
Background Rules
Rule Name Cstate Mstate Next Cstate Next Mstate
CRF-Cache a =2 sache Cell(a,v) Cell(a,v,Clean) Cell(a,v)
CRF-Writeback Cell(a,v,Dirty) Cell(a,-) Cell(a,v,Clean) Cell(a,v)
CRF-Purge Cell(a,-,Clean) Cell(a,v) a =2 sache Cell(a,v)
Figure 3.4: Summary of CR Rules
producer performs a commit operation to guarantee that the modi ed data has been written
back to the memory, while the consumer performs a reconcile operation to guarantee that the
stale copy, if any, has been purged from the sache so that subsequent load operations must
retrieve the data from the memory (see Figure 3.3).
Cache, Writeback and Purge Rules: Asache can obtain a Clean copy from the memory,
if the address is not cached at the time (thus no sache can contain more than one copy for the
same address). A Dirty copy can be written back to the memory, after which thesache state
becomes Clean. A Clean copy can be purged from the sache at any time, but cannot be written
back to the memory. These rules are also called background rules, since they can be applied
even though no instruction is executed by any processor.
CRF-Cache Rule
Sys(mem, Site(sache, pmb, mpb, proc) j sites) if a =2 sache
! Sys(mem, Site(Cell(a,mem[a],Clean) j sache, pmb, mpb, proc) j sites)
CRF-Writeback Rule
Sys(mem, Site(Cell(a,v,Dirty) j sache, pmb, mpb, proc) j sites)
! Sys(mem[a:=v], Site(Cell(a,v,Clean) j sache, pmb, mpb, proc) j sites)
CRF-Purge Rule
Site(Cell(a,-,Clean) j sache, pmb, mpb, proc)
! Site(sache, pmb, mpb, proc)
The CR rules are summarized in Figure 3.4. The seven rules are classi ed into two cate-
gories: the processor rules and the background rules. Each processor rule processes a memory
instruction to completion. When an instruction is completed (retired), it is removed from
the processor-to-memory bu er and the corresponding data or acknowledgment is sent to the
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