Design and Verification of Adaptive Cache Coherence Protocols ...

More documents

Recommendations

Info

Processor Rules Rule Name Instruction Cstate Action Next Cstate GCRF-Loadl Loadl(a) Cell(a,v,cs) retire Cell(a,v,cs) GCRF-Storel Storel(a,v) Cell(a,-,-) retire Cell(a,v,S) GCRF-Commit Commit(a) Cell(a,v, ) retire Cell(a,v, ) a =2 sache retire a =2 sache GCRF-Reconcile Reconcile(a) Cell(a,v,cs) (cs 6= ) retire Cell(a,v,cs) a =2 sache retire a =2 sache Background Rules Rule Name Cstate Mstate Next Cstate Next Mstate GCRF-Cache a =2 sache Cell(a,v) Cell(a,v, ) Cell(a,v) GCRF-Writeback Cell(a,v,id jcs) Cell(a,-) Cell(a,v,cs) Cell(a,v) GCRF-Purge Cell(a,-, ) Cell(a,v) a =2 sache Cell(a,v) GCRF-Writeback Rule Figure 3.8: Summary of GCRF Rules (except reordering rules) Site(id , mem, Cell(a,v,id jcs) j sache, pmb, mpb, proc) ! Site(id , mem[a:=v], Cell(a,v,cs) j sache, pmb, mpb, proc) Site(id , mem, Cell(a,v,id1jcs) j sache, pmb, mpb, proc) j Site(id1, mem1, sache1, pmb1, mpb1, proc1) ! Site(id , mem, Cell(a,v,cs) j sache, pmb, mpb, proc) j Site(id1, mem1[a:=v], sache1, pmb1, mpb1, proc1) GCRF-Purge Rule Site(id , mem, Cell(a,-, ) j sache, pmb, mpb, proc) ! Site(id , mem, sache, pmb, mpb, proc) The GCRF model also allows instructions to be reordered the reordering rules of CRF all remain unchanged. The GCRF rules are summarized in Figure 3.8. In the tabular description, for the cache and purge rules, the memory state re ects the memory cell in the same site as the sache cell for the writeback rule, the memory state re ects the memory cell in site id . The GCRF model also allows instructions to be reordered the reordering rules are exactly thesameasthose of CRF. In addition, we can de ne a new commit instruction that commits an address with respect to an individual memory. The semantics of the instruction can be speci ed as follows: Site(id , mem, sache, ht,Commit(a,id )ipmb, mpb, proc) if Cell(a,-,id j-) =2 sache ! Site(id , mem, sache, pmb, mpbjht,Acki, proc) The Commit(a,id ) instruction guarantees that the dirty copy is written back to the memory at site id before the instruction completes. The normal commit instruction can be de ned by a sequence of the ner-grain commit instructions. 64
Chapter 4 The Base Cache Coherence Protocol The Base protocol is the most straightforward implementation of the CRF model. An attractive characteristic of Base is its simplicity: no state needs to be maintained at the memory side. In Base, a commit operation on a dirty cell forces the data to be written back to the memory, and a reconcile operation on a clean cell forces the data to be purged from the cache. This is ideal for programs in which only necessary commit and reconcile operations are performed. In this chapter, we rst present a novel protocol design methodology called Imperative-&- Directive that will be used throughout this thesis. Section 4.2 describes the system con guration of the Base protocol and gives the message passing rules for non-FIFO and FIFO networks. We de ne the imperative rules of Base in Section 4.3, and present the complete Base protocol in Section 4.4. Section 4.5 proves the soundness of Base by showing that the imperative Base rules can be simulated in CRF Section 4.6 proves the liveness of Base by showing that each processor can always make progress (that is, a memory instruction can always be completed eventually). 4.1 The Imperative-&-Directive Design Methodology In spite of the development of various cache coherence protocols, it is di cult to discern any methodology that has guided the design of existing protocols. A major source of complexity in protocol design is that the designer often deals with many di erent issues simultaneously. Are coherence states being maintained correctly? Is it possible that a cache miss may never be serviced? What is the consequence if messages get reordered in the network? How to achieve better adaptivity for programs with di erent access patterns? Answering such questions can be di cult for sophisticated protocols with various optimizations. The net result is that protocol design is viewed as an enigma, and even the designer is not totally con dent of his or her understanding of the protocol behavior. We propose a two-stage design methodology called Imperative-&-Directive that separates soundness and liveness concerns in the design process (see Figure 4.1). Soundness ensures that 65
Page 1:
CSAIL Computer Science and Artifici
Page 5:
Design and Veri cation of Adaptive
Page 8 and 9:
I am truly grateful to my parents f
Page 10 and 11:
4 The Base Cache Coherence Protocol
Page 13 and 14:
List of Figures 1.1 Impact of Archi
Page 15 and 16: Chapter 1 Introduction Shared memor
Page 17 and 18: transparent and exposed only for lo
Page 19 and 20: Example 1: Can both registers r1 an
Page 21 and 22: and release locks, which guard ever
Page 23 and 24: that are interconnected with an o -
Page 25 and 26: although various techniques have be
Page 27 and 28: y showing that each processor can a
Page 29 and 30: s1 if p (s1) ! s2 where s1 and s2 a
Page 31 and 32: Program counter (pc) +1 Instruction
Page 33 and 34: Branch target buffer (btb) Program
Page 35 and 36: instruction is waiting to be dispat
Page 37 and 38: Current State: Proc(ia, rf , rob, b
Page 39 and 40: Rule Name mem pmb mpb Next mem Next
Page 41 and 42: Specification Implementation t 1 B
Page 43 and 44: Intuitively, \2P " means that \P is
Page 45 and 46: (a) (b) PC 1005 PC 2000 Instruction
Page 47 and 48: ewritten to s2 according to rule R.
Page 49 and 50: It can be shown that the relaxed di
Page 51 and 52: Chapter 3 The Commit-Reconcile & Fe
Page 53 and 54: Producer Storel(a,v) Commit(a) Cons
Page 55 and 56: Commit/Reconcile Purge Loadl/Commit
Page 57 and 58: instructions, because of the lack o
Page 59 and 60: CRF-Relaxed-Commit Rule Site(sache,
Page 61 and 62: 3.4 Universality of the CRF Model M
Page 63 and 64: Translation from CRF to PSO: The Fe
Page 65: proc proc proc pmb mpb pmb mpb pmb
Page 69 and 70: can be classi ed into two non-overl
Page 71 and 72: arbitrarily in an outgoing queue (t
Page 73 and 74: 4.3 The Imperative Rules of the Bas
Page 75 and 76: Imperative Processor Rules Instruct
Page 77 and 78: Figure 4.5 de nes the rules of the
Page 79 and 80: 4.5.2 Mapping from Base to CRF We d
Page 81 and 82: Base Imperative Rule CRF Rule IP1 (
Page 83 and 84: Base Rule Base Imperative Rule P1 I
Page 85 and 86: eceives a CacheReq message, it will
Page 87 and 88: e completed if it has an in nite nu
Page 89 and 90: SYS Sys(MSITE, SITEs) System MSITE
Page 91 and 92: Commit/Reconcile C-Receive-WbAck Ru
Page 93 and 94: message can be resumed eventually.
Page 95 and 96: If the memory state shows that the
Page 97 and 98: 5.3.3 FIFO Message Passing The live
Page 99 and 100: Figure 5.7 gives the M-engine rules
Page 101 and 102: Backward-Message-Cache-to-Mem-for-W
Page 103 and 104: 5.4.3 Simulation of WP in CRF Theor
Page 105 and 106: WP Imperative Rule CRF Rules IP1 (L
Page 107 and 108: WP Rule WP Imperative & Directive R
Page 109 and 110: (4) Msg(H,id ,Cache,a,-)" 2 Cin id(
Page 111 and 112: This completes the proof according
Page 113 and 114: emains as CachePending, there mustb
Page 115 and 116: M-engine Rules Msg from id Mstate A
Page 117 and 118:
Chapter 6 The Migratory Cache Coher
Page 119 and 120:
Commit/Reconcile Send Purge Loadl/C
Page 121 and 122:
Mandatory Processor Rules Instructi
Page 123 and 124:
while the memory sends a FlushReq m
Page 125 and 126:
Lemma 38 D is strongly terminating
Page 127 and 128:
Migratory Imperative Rule CRF Rules
Page 129 and 130:
Cell(a,v,C[id ]) 2 Mem(s) _ Cell(a,
Page 131 and 132:
According to Theorem-C and Lemma 45
Page 133 and 134:
CacheReq message. In the latter cas
Page 135 and 136:
Chapter 7 Cachet: A Seamless Integr
Page 137 and 138:
7.1.1 Putting Things Together It is
Page 139 and 140:
Writeback Operations In Cachet, a w
Page 141 and 142:
Composite Message Equivalent Sequen
Page 143 and 144:
Imperative Processor Rules Instruct
Page 145 and 146:
Invalid Commit/Reconcile Receive Ca
Page 147 and 148:
Composite Imperative C-engine Rules
Page 149 and 150:
7.4 The Cachet Cache Coherence Prot
Page 151 and 152:
Voluntary C-engine Rules Cstate Act
Page 153 and 154:
The memory processes an incoming Ca
Page 155 and 156:
The inaccuracy of memory states can
Page 157 and 158:
C-engine Rule of Cachet Deriving Im
Page 159 and 160:
Composite Mandatory Processor Rules
Page 161 and 162:
memory regions simultaneously. In a
Page 163 and 164:
Chapter 8 Conclusions This thesis h
Page 165 and 166:
and heuristic policies. Mandatory r
Page 167 and 168:
technique can be used to allow a ca
Page 169 and 170:
Voluntary C-engine Rules Cstate Act
Page 171 and 172:
FIFO Message Passing msg1 msg2 msg2
Page 173 and 174:
[13] J. K. Archibald. The Cache Coh
Page 175 and 176:
[41] A. Erlichson, N. Nuckolls, G.
Page 177 and 178:
[71] J. Kuskin, D. Ofelt, M. Heinri
Page 179 and 180:
[101] F. Pong and M. Dubois. A New
show all

Design and Verification of Adaptive Cache Coherence Protocols ...

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?