Design and Verification of Adaptive Cache Coherence Protocols ...

This completes the proof according to Theorem-A. 2
The proof above can be explained in a more intuitive way. The memory sends a PurgeReq
message to cache id each time it changes the memory state to T[id j-,-]. When the PurgeReq
message is received at cache id , if the cache state is Clean or Dirty, the cache sends a Purge or
Wb message to the memory otherwise the cache ignores the PurgeReq message. In the latter
case, if the memory state remains as T[id j-,-], there must be a Purge or Wb message in transit
from cache id to the memory according to Lemma 26 (note that the PurgeReq message has no
following message since the memory cannot send any message to cache id while the memory
state is T[id j-,-], and FIFO message passing guarantees that any preceding message must be
received before the PurgeReq message is received). When the memory receives the Purge or
Wb message, it removes the cache identi er from the directory.
Lemma 30 includes invariants about transient memory states. Invariant (1) ensures that the
directory of a transient state will eventually become empty while each suspended writeback
message remains una ected. The proof is based on induction on the number of cache identi ers
in the directory. It can be shown by checking each WP rule that suspended messages cannot
be a ected before the directory becomes empty. Invariant (2) ensures that a transient memory
state will eventually become a stable memory state. The proof follows from the weak fairness
of Rule MM11. This is critical to ensure that a stalled CacheReq message will be processed
eventually.
Lemma 30 Given a WP sequence ,
(1) Cell(a,-,T[-,(id ,-)j-]) 2 Mem( ) Cell(a,-,T[ ,(id ,-)j-]) 2 Mem( )
(2) Cell(a,-,T[-,-]) 2 Mem( ) Cell(a,-,C[-]) 2 Mem( )
Lemma 31 ensures that any incoming message can become the rst message regarding the
address in the incoming queue (so that it can be processed by the corresponding protocol
engine). This is a general form of Lemma 28.
Lemma 31 Given a WP sequence ,
(1) msg 2 Cin id( ) msg" 2 Cin id( )
(2) msg 2 Min( ) msg" 2 Min( )
Lemma 32 ensures that if an address is cached in the CachePending state, the cache state will
become Clean eventually. This is important to guarantee thatacache miss can be serviced in
nite time.
Lemma 32 Given a WP sequence ,
Cell(a,-,CachePending) 2 Cache id( ) Cell(a,-,Clean) 2 Cache id( )
Proof We rst show some properties that are needed for the proof all the properties can be
veri ed by simplychecking the WP rules.
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