Design and Verification of Adaptive Cache Coherence Protocols ...

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Appendix A The Cachet Protocol Speci cation Mandatory Processor Rules Instruction Cstate Action Next Cstate Loadl(a) Cell(a,v,Cleanb) retire Cell(a,v,Cleanb) SF Cell(a,v,Dirtyb) retire Cell(a,v,Dirtyb) SF Cell(a,v,Cleanw) retire Cell(a,v,Cleanw) SF Cell(a,v,Dirtyw) retire Cell(a,v,Dirtyw) SF Cell(a,v,Cleanm) retire Cell(a,v,Cleanm) SF Cell(a,v,Dirtym) retire Cell(a,v,Dirtym) SF Cell(a,v,WbPending) stall Cell(a,v,WbPending) Cell(a,-,CachePending) stall Cell(a,-,CachePending) a =2 cache stall, hCacheReq,ai !H Cell(a,-,CachePending) Storel(a,v) Cell(a,-,Cleanb) retire Cell(a,v,Dirtyb) SF Cell(a,-,Dirtyb) retire Cell(a,v,Dirtyb) SF Cell(a,-,Cleanw) retire Cell(a,v,Dirtyw) SF Cell(a,-,Dirtyw) retire Cell(a,v,Dirtyw) SF Cell(a,-,Cleanm) retire Cell(a,v,Dirtym) SF Cell(a,-,Dirtym) retire Cell(a,v,Dirtym) SF Cell(a,v1,WbPending) stall Cell(a,v1,WbPending) Cell(a,-,CachePending) stall Cell(a,-,CachePending) a =2 cache stall, hCacheReq,ai !H Cell(a,-,CachePending) Commit(a) Cell(a,v,Cleanb) retire Cell(a,v,Cleanb) SF Cell(a,v,Dirtyb) stall, hWbb,a,vi!H Cell(a,v,WbPending) Cell(a,v,Cleanw) retire Cell(a,v,Cleanw) SF Cell(a,v,Dirtyw) stall, hWbw,a,vi!H Cell(a,v,WbPending) Cell(a,v,Cleanm) retire Cell(a,v,Cleanm) SF Cell(a,v,Dirtym) retire Cell(a,v,Dirtym) SF Cell(a,v,WbPending) stall Cell(a,v,WbPending) Cell(a,-,CachePending) stall Cell(a,-,CachePending) a =2 cache retire a =2 cache SF Reconcile(a) Cell(a,-,Cleanb) retire a =2 cache SF Cell(a,v,Dirtyb) retire Cell(a,v,Dirtyb) SF Cell(a,v,Cleanw) retire Cell(a,v,Cleanw) SF Cell(a,v,Dirtyw) retire Cell(a,v,Dirtyw) SF Cell(a,v,Cleanm) retire Cell(a,v,Cleanm) SF Cell(a,v,Dirtym) retire Cell(a,v,Dirtym) SF Cell(a,v,WbPending) stall Cell(a,v,WbPending) Cell(a,-,CachePending) stall Cell(a,-,CachePending) a =2 cache retire a =2 cache SF Figure A.1: Cachet: The Processor Rules 166
Voluntary C-engine Rules Cstate Action Next Cstate Cell(a,-,Cleanb) a =2 cache Cell(a,v,Dirtyb) hWbb,a,vi!H Cell(a,v,WbPending) Cell(a,v,Cleanw) hDownwb,ai!H Cell(a,v,Cleanb) Cell(a,v,Dirtyw) hDownwb,ai!H Cell(a,v,Dirtyb) hWbw,a,vi!H Cell(a,v,WbPending) Cell(a,v,Cleanm) hDownmw,ai!H Cell(a,v,Cleanw) hDownmb,ai!H Cell(a,v,Cleanb) Cell(a,v,Dirtym) hDownVmw,a,vi!H Cell(a,v,Cleanw) hDownVmb,a,vi!H Cell(a,v,Cleanb) a =2 cache hCacheReq,ai !H Cell(a,-,CachePending) Mandatory C-engine Rules Msg from H Cstate Action Next Cstate hCacheb,a,vi Cell(a,-,CachePending) Cell(a,v,Cleanb) hCachew,a,vi Cell(a,-,Cleanb) Cell(a,v,Cleanw) Cell(a,v1,Dirtyb) Cell(a,v1,Dirtyw) Cell(a,v1,WbPending) Cell(a,v1,WbPending) Cell(a,-,CachePending) Cell(a,v,Cleanw) a =2 cache Cell(a,v,Cleanw) hCachem,a,vi Cell(a,-,Cleanb) Cell(a,v,Cleanm) Cell(a,v1,Dirtyb) Cell(a,v1,Dirtym) Cell(a,v1,WbPending) Cell(a,v1,WbPending) Cell(a,-,CachePending) Cell(a,v,Cleanm) a =2 cache Cell(a,v,Cleanm) hUpwm,ai Cell(a,v,Cleanb) Cell(a,v,Cleanb) Cell(a,v,Dirtyb) Cell(a,v,Dirtyb) Cell(a,v,Cleanw) Cell(a,v,Cleanm) Cell(a,v,Dirtyw) Cell(a,v,Dirtym) Cell(a,v,WbPending) Cell(a,v,WbPending) Cell(a,-,CachePending) Cell(a,-,CachePending) a =2 cache a =2 cache hWbAckb,ai Cell(a,v,WbPending) Cell(a,v,Cleanb) hWbAckw,ai Cell(a,v,WbPending) Cell(a,v,Cleanw) hWbAckm,ai Cell(a,v,WbPending) Cell(a,v,Cleanm) hDownReqwb,ai Cell(a,v,Cleanb) Cell(a,v,Cleanb) Cell(a,v,Dirtyb) Cell(a,v,Dirtyb) Cell(a,v,Cleanw) hDownwb,ai!H Cell(a,v,Cleanb) Cell(a,v,Dirtyw) hDownwb,ai!H Cell(a,v,Dirtyb) Cell(a,v,WbPending) Cell(a,v,WbPending) Cell(a,-,CachePending) Cell(a,-,CachePending) a =2 cache a =2 cache hDownReqmw,ai Cell(a,v,Cleanb) Cell(a,v,Cleanb) Cell(a,v,Dirtyb) Cell(a,v,Dirtyb) Cell(a,v,Cleanw) Cell(a,v,Cleanw) Cell(a,v,Dirtyw) Cell(a,v,Dirtyw) Cell(a,v,Cleanm) hDownmw,ai!H Cell(a,v,Cleanw) Cell(a,v,Dirtym) hDownVmw,a,vi!H Cell(a,v,Cleanw) Cell(a,v,WbPending) Cell(a,v,WbPending) Cell(a,-,CachePending) Cell(a,-,CachePending) a =2 cache a =2 cache hDownReqmb,ai Cell(a,v,Cleanb) Cell(a,v,Cleanb) Cell(a,v,Dirtyb) Cell(a,v,Dirtyb) Cell(a,v,Cleanw) hDownwb,ai!H Cell(a,v,Cleanb) Cell(a,v,Dirtyw) hDownwb,ai!H Cell(a,v,Dirtyb) Cell(a,v,Cleanm) hDownmb,ai!H Cell(a,v,Cleanb) Cell(a,v,Dirtym) hDownVmb,a,vi!H Cell(a,v,Cleanb) Cell(a,v,WbPending) Cell(a,v,WbPending) Cell(a,-,CachePending) Cell(a,-,CachePending) a =2 cache a =2 cache Figure A.2: Cachet: The Cache Engine Rules 167
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CSAIL Computer Science and Artifici
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Design and Veri cation of Adaptive
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I am truly grateful to my parents f
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4 The Base Cache Coherence Protocol
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List of Figures 1.1 Impact of Archi
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Chapter 1 Introduction Shared memor
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transparent and exposed only for lo
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Example 1: Can both registers r1 an
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and release locks, which guard ever
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that are interconnected with an o -
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although various techniques have be
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y showing that each processor can a
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s1 if p (s1) ! s2 where s1 and s2 a
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Program counter (pc) +1 Instruction
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Branch target buffer (btb) Program
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instruction is waiting to be dispat
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Current State: Proc(ia, rf , rob, b
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Rule Name mem pmb mpb Next mem Next
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Specification Implementation t 1 B
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Intuitively, \2P " means that \P is
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(a) (b) PC 1005 PC 2000 Instruction
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ewritten to s2 according to rule R.
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It can be shown that the relaxed di
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Chapter 3 The Commit-Reconcile & Fe
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Producer Storel(a,v) Commit(a) Cons
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Commit/Reconcile Purge Loadl/Commit
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instructions, because of the lack o
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CRF-Relaxed-Commit Rule Site(sache,
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3.4 Universality of the CRF Model M
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Translation from CRF to PSO: The Fe
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proc proc proc pmb mpb pmb mpb pmb
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Chapter 4 The Base Cache Coherence
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can be classi ed into two non-overl
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arbitrarily in an outgoing queue (t
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4.3 The Imperative Rules of the Bas
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Imperative Processor Rules Instruct
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Figure 4.5 de nes the rules of the
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4.5.2 Mapping from Base to CRF We d
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Base Imperative Rule CRF Rule IP1 (
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Base Rule Base Imperative Rule P1 I
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eceives a CacheReq message, it will
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e completed if it has an in nite nu
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SYS Sys(MSITE, SITEs) System MSITE
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Commit/Reconcile C-Receive-WbAck Ru
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message can be resumed eventually.
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If the memory state shows that the
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5.3.3 FIFO Message Passing The live
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Figure 5.7 gives the M-engine rules
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Backward-Message-Cache-to-Mem-for-W
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5.4.3 Simulation of WP in CRF Theor
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WP Imperative Rule CRF Rules IP1 (L
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WP Rule WP Imperative & Directive R
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(4) Msg(H,id ,Cache,a,-)" 2 Cin id(
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This completes the proof according
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emains as CachePending, there mustb
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M-engine Rules Msg from id Mstate A
Page 117 and 118: Chapter 6 The Migratory Cache Coher
Page 119 and 120: Commit/Reconcile Send Purge Loadl/C
Page 121 and 122: Mandatory Processor Rules Instructi
Page 123 and 124: while the memory sends a FlushReq m
Page 125 and 126: Lemma 38 D is strongly terminating
Page 127 and 128: Migratory Imperative Rule CRF Rules
Page 129 and 130: Cell(a,v,C[id ]) 2 Mem(s) _ Cell(a,
Page 131 and 132: According to Theorem-C and Lemma 45
Page 133 and 134: CacheReq message. In the latter cas
Page 135 and 136: Chapter 7 Cachet: A Seamless Integr
Page 137 and 138: 7.1.1 Putting Things Together It is
Page 139 and 140: Writeback Operations In Cachet, a w
Page 141 and 142: Composite Message Equivalent Sequen
Page 143 and 144: Imperative Processor Rules Instruct
Page 145 and 146: Invalid Commit/Reconcile Receive Ca
Page 147 and 148: Composite Imperative C-engine Rules
Page 149 and 150: 7.4 The Cachet Cache Coherence Prot
Page 151 and 152: Voluntary C-engine Rules Cstate Act
Page 153 and 154: The memory processes an incoming Ca
Page 155 and 156: The inaccuracy of memory states can
Page 157 and 158: C-engine Rule of Cachet Deriving Im
Page 159 and 160: Composite Mandatory Processor Rules
Page 161 and 162: memory regions simultaneously. In a
Page 163 and 164: Chapter 8 Conclusions This thesis h
Page 165 and 166: and heuristic policies. Mandatory r
Page 167: technique can be used to allow a ca
Page 171 and 172: FIFO Message Passing msg1 msg2 msg2
Page 173 and 174: [13] J. K. Archibald. The Cache Coh
Page 175 and 176: [41] A. Erlichson, N. Nuckolls, G.
Page 177 and 178: [71] J. Kuskin, D. Ofelt, M. Heinri
Page 179 and 180: [101] F. Pong and M. Dubois. A New
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