Design and Verification of Adaptive Cache Coherence Protocols ...

3.4 Universality of the CRF Model
Most relaxed or weaker memory models have arisen as a consequence of speci c architectural
optimizations in the implementation of memory access instructions, rather than from some
high-level design. Di erent manufacturers have di erent memory models even the same man-
ufacturer can have di erent memory models for di erent generations of machines. The CRF
model can be used to eliminate the modele de l'annee aspect of many existing memory mod-
els. Programs written under sequential consistency and various weaker memory models can be
translated into CRF programs without incurring unnecessary overhead. The translations can
be taken as precise de nitions of the often imprecise descriptions of the semantics of memory in-
structions given by the manufacturers. On the other hand, CRF programs can be mapped back
to programs that can run e ciently on existing microprocessors. This section demonstrates the
upward and downward compatibility of the CRF model.
The upward compatibility refersto the the ability to run existing programs correctly and
e ciently on a CRF machine. As an example, we show translation schemes for SC, Sparc's TSO,
PSO and RMO models and the IBM 370's model. Weaker memory models that allow memory
instructions to be reordered usually provide memory barrier or fence instructions that can be
used to enforce necessary ordering. Some machines such as IBM 370 have no explicit barrier
instructions but instead rely on the implicit barrier-like semantics of some special instructions.
We still refer to such instructions as memory barriers (Membar) in the translation schemes.
The translation from SC to CRF is simple because SC requires strict in-order and atomic
execution of load and store instructions.
Loadsc(a) Fencerr( ,a) Fencewr( ,a) Reconcile(a) Loadl(a)
Storesc(a,v) Fencerw( ,a) Fenceww( ,a) Storel(a,v) Commit(a)
The translation guarantees that the resulting CRF program has exactly the same behavior
as the SC program. Note that each fence can be replaced by a coarse-grain instruction
Fence( , ) without eliminating any program behavior.
TSO allows a load to be performed before outstanding stores complete, which virtually
models FIFO write-bu ers. It also allows a load to retrieve the data from an outstanding
store to the same address before the data is observable to other processors.
Loadtso(a) Fencerr( ,a) Reconcile(a) Loadl(a)
Storetso(a,v) Fencerw( ,a) Fenceww( ,a) Storel(a,v) Commit(a)
Membar-liketso Fencewr( , )
The translation places a Fencerr before each Reconcile-Loadl pair to ensure the load-load
ordering, and a Fencerw and a Fenceww before each Storel-Commit pair to ensure the
load-store and store-store ordering. The Membar instruction is simply translated into a
write-read fence for all the addresses.
PSO allows a load to overtake outstanding stores and in addition, a store to overtake
other outstanding stores. This models non-FIFO write bu ers. The short-circuiting is
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