Design and Verification of Adaptive Cache Coherence Protocols ...

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5.5 The WP Protocol : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 92 5.6 Cache State Transitions of WP : : : : : : : : : : : : : : : : : : : : : : : : : : : : 94 5.7 Simpli ed Memory Engine Rules of WP : : : : : : : : : : : : : : : : : : : : : : : 96 5.8 Simulation of WP in CRF : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 103 5.9 Derivation of WP from Imperative & Directive Rules : : : : : : : : : : : : : : : : 105 5.10 Memory Engine Rules of an Update Protocol : : : : : : : : : : : : : : : : : : : : 113 5.11 An Alternative Writer-Push Protocol : : : : : : : : : : : : : : : : : : : : : : : : : 114 6.1 System Con guration of Migratory : : : : : : : : : : : : : : : : : : : : : : : : : : 116 6.2 Cache State Transitions of Migratory's Imperative Operations : : : : : : : : : : : 117 6.3 Imperative Rules of Migratory : : : : : : : : : : : : : : : : : : : : : : : : : : : : 118 6.4 The Migratory Protocol : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 119 6.5 Cache State Transitions of Migratory : : : : : : : : : : : : : : : : : : : : : : : : : 120 6.6 Simulation of Migratory in CRF : : : : : : : : : : : : : : : : : : : : : : : : : : : 125 6.7 Derivation of Migratory from Imperative & Directive Rules : : : : : : : : : : : : 126 7.1 Di erent Treatment of Commit, Reconcile and Cache Miss : : : : : : : : : : : : : 134 7.2 Downgrade and Upgrade Operations : : : : : : : : : : : : : : : : : : : : : : : : : 136 7.3 Protocol Messages of Cachet : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 138 7.4 Composite Messages of Cachet : : : : : : : : : : : : : : : : : : : : : : : : : : : : 139 7.5 Imperative Processor Rules of Cachet : : : : : : : : : : : : : : : : : : : : : : : : 141 7.6 Imperative Cache Engine Rules of Cachet : : : : : : : : : : : : : : : : : : : : : : 142 7.7 Cache State Transitions of Cachet : : : : : : : : : : : : : : : : : : : : : : : : : : 143 7.8 Imperative Memory Engine Rules of Cachet : : : : : : : : : : : : : : : : : : : : : 144 7.9 Composite Imperative Rules of Cachet : : : : : : : : : : : : : : : : : : : : : : : : 145 7.10 Simulation of Composite Imperative Rules of Cachet : : : : : : : : : : : : : : : : 146 7.11 Processor Rules of Cachet : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 148 7.12 Cache Engine Rules of Cachet : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 149 7.13 Memory Engine Rules of Cachet (Rule MM1 is strongly fair) : : : : : : : : : : : 150 7.14 Derivation of Processor Rules of Cachet : : : : : : : : : : : : : : : : : : : : : : : 154 7.15 Derivation of Cache Engine Rules of Cachet : : : : : : : : : : : : : : : : : : : : : 155 7.16 Derivation of Memory Engine Rules of Cachet : : : : : : : : : : : : : : : : : : : : 156 7.17 Composite Rules of Cachet : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 157 7.18 Simulation of Composite Rules of Cachet : : : : : : : : : : : : : : : : : : : : : : 158 A.1 Cachet: The Processor Rules : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 166 A.2 Cachet: The Cache Engine Rules : : : : : : : : : : : : : : : : : : : : : : : : : : : 167 A.3 Cachet: The Memory Engine Rules : : : : : : : : : : : : : : : : : : : : : : : : : : 168 A.4 FIFO Message Passing and Bu er Management : : : : : : : : : : : : : : : : : : : 169 12
Chapter 1 Introduction Shared memory multiprocessor systems provide a global memory image so that processors run- ning parallel programs can exchange information and synchronize with one another by access- ing shared variables. In large scale shared memory systems, the physical memory is typically distributed across di erent sites to achieve better performance. Distributed Shared Memory (DSM) systems implement the shared memory abstraction with a large number of processors connected by a network, combining the scalability ofnetwork-based architectures with the con- venience of shared memory programming. Caching technique allows shared variables to be replicated in multiple sites simultaneously to reduce memory access latency. DSM systems rely on cache coherence protocols to ensure that each processor can observe the semantic e ect of memory access operations performed by another processor in time. The design of cache coherence protocols plays a crucial role in the construction of shared memory systems because of its profound impact on the overall performance and implementation complexity. It is also one of the most complicated problems because e cient cache coherence protocols usually incorporate various optimizations, especially for cache coherence protocols that implement relaxed memory models. This thesis elaborates on several relevant issues about cache coherence protocols for DSM systems: what memory model should be supported, what adaptivity canbeprovided and how sophisticated and adaptive cache coherence protocols can be designed and veri ed. A shared memory system implements a memory model that de nes the semantics of memory access instructions. An ideal memory model should allow e cient and scalable implementa- tions while still have simple semantics for the architect and the compiler writer to reason about. Although various memory models have been proposed, there is little consensus on a memory model that shared memory systems should support. Sequential consistency is easy for program- mers to understand and use, but it often prohibits many architectural and compiler optimizations. On the other hand, relaxed memory models may allow various optimizations, but their ever-changing and implementation-dependent de nitions have created a situation where even experienced architects may have di culty articulating precisely the impact of these memory models on program behaviors. 13
Page 1: CSAIL Computer Science and Artifici
Page 5: Design and Veri cation of Adaptive
Page 8 and 9: I am truly grateful to my parents f
Page 10 and 11: 4 The Base Cache Coherence Protocol
Page 13: List of Figures 1.1 Impact of Archi
Page 17 and 18: transparent and exposed only for lo
Page 19 and 20: Example 1: Can both registers r1 an
Page 21 and 22: and release locks, which guard ever
Page 23 and 24: that are interconnected with an o -
Page 25 and 26: although various techniques have be
Page 27 and 28: y showing that each processor can a
Page 29 and 30: s1 if p (s1) ! s2 where s1 and s2 a
Page 31 and 32: Program counter (pc) +1 Instruction
Page 33 and 34: Branch target buffer (btb) Program
Page 35 and 36: instruction is waiting to be dispat
Page 37 and 38: Current State: Proc(ia, rf , rob, b
Page 39 and 40: Rule Name mem pmb mpb Next mem Next
Page 41 and 42: Specification Implementation t 1 B
Page 43 and 44: Intuitively, \2P " means that \P is
Page 45 and 46: (a) (b) PC 1005 PC 2000 Instruction
Page 47 and 48: ewritten to s2 according to rule R.
Page 49 and 50: It can be shown that the relaxed di
Page 51 and 52: Chapter 3 The Commit-Reconcile & Fe
Page 53 and 54: Producer Storel(a,v) Commit(a) Cons
Page 55 and 56: Commit/Reconcile Purge Loadl/Commit
Page 57 and 58: instructions, because of the lack o
Page 59 and 60: CRF-Relaxed-Commit Rule Site(sache,
Page 61 and 62: 3.4 Universality of the CRF Model M
Page 63 and 64: Translation from CRF to PSO: The Fe
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proc proc proc pmb mpb pmb mpb pmb
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Chapter 4 The Base Cache Coherence
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can be classi ed into two non-overl
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arbitrarily in an outgoing queue (t
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4.3 The Imperative Rules of the Bas
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Imperative Processor Rules Instruct
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Figure 4.5 de nes the rules of the
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4.5.2 Mapping from Base to CRF We d
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Base Imperative Rule CRF Rule IP1 (
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Base Rule Base Imperative Rule P1 I
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eceives a CacheReq message, it will
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e completed if it has an in nite nu
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SYS Sys(MSITE, SITEs) System MSITE
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Commit/Reconcile C-Receive-WbAck Ru
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message can be resumed eventually.
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If the memory state shows that the
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5.3.3 FIFO Message Passing The live
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Figure 5.7 gives the M-engine rules
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Backward-Message-Cache-to-Mem-for-W
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5.4.3 Simulation of WP in CRF Theor
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WP Imperative Rule CRF Rules IP1 (L
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WP Rule WP Imperative & Directive R
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(4) Msg(H,id ,Cache,a,-)" 2 Cin id(
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This completes the proof according
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emains as CachePending, there mustb
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M-engine Rules Msg from id Mstate A
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Chapter 6 The Migratory Cache Coher
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Commit/Reconcile Send Purge Loadl/C
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Mandatory Processor Rules Instructi
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while the memory sends a FlushReq m
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Lemma 38 D is strongly terminating
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Migratory Imperative Rule CRF Rules
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Cell(a,v,C[id ]) 2 Mem(s) _ Cell(a,
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According to Theorem-C and Lemma 45
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CacheReq message. In the latter cas
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Chapter 7 Cachet: A Seamless Integr
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7.1.1 Putting Things Together It is
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Writeback Operations In Cachet, a w
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Composite Message Equivalent Sequen
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Imperative Processor Rules Instruct
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Invalid Commit/Reconcile Receive Ca
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Composite Imperative C-engine Rules
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7.4 The Cachet Cache Coherence Prot
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Voluntary C-engine Rules Cstate Act
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The memory processes an incoming Ca
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The inaccuracy of memory states can
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C-engine Rule of Cachet Deriving Im
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Composite Mandatory Processor Rules
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memory regions simultaneously. In a
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Chapter 8 Conclusions This thesis h
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and heuristic policies. Mandatory r
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technique can be used to allow a ca
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Voluntary C-engine Rules Cstate Act
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FIFO Message Passing msg1 msg2 msg2
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[13] J. K. Archibald. The Cache Coh
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[41] A. Erlichson, N. Nuckolls, G.
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[71] J. Kuskin, D. Ofelt, M. Heinri
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[101] F. Pong and M. Dubois. A New
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