Design and Verification of Adaptive Cache Coherence Protocols ...

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[28] S. Chandra, B. Richard, and J. R. Larus. Teapot: Language support for writing memory coherence protocols. In Proceedings of the SIGPLAN Conference on Programming Language Design and Implementation, May 1996. [29] D. Chiou. Extending the Reach of Microprocessors: Column and Curious Caching. PhD Dissertation, Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Sept. 1999. [30] E. Clarke, E. Emerson, and A. Sistla. Automatic Veri cation of Finite-State Concurrent Systems using Temporal Logic Speci cations. ACM Transactions on Programming Languages and Systems, 8(2):244{263, Apr. 1986. [31] A. E. Condon, M. D. Hill, M. Plakal, and D. J. Sorin. Using Lamport Clocks to Reason About Relaxed Memory Models. In Proceedings of the 5th International Symposium on High-Performance Computer Architecture, 1999. [32] B. Cook, J. Launchbury, and J. Matthews. Specifying Superscalar Microprocessors in Hawk. In Proceedings of the Workshop on Formal Techniques for Hardware and Hardwarelike Systems, Marstrand, Sweden, June 1998. [33] F. Corella, J. M. Stone, and C. Barton. A Formal Speci cation of the PowerPC Shared Memory Architecture. Research Report 18638 (81566), IBM Research Division, 1993. [34] A. L. Cox and R. J. Fowler. Adaptive Cache Coherency for Detecting Migratory Shared Data. In Proceedings of the 20th International Symposium on Computer Architecture, May 1993. [35] D. L. Dill, A. J. Drexler, A. J. Hu, and C. H. Yang. Protocol Veri cation as a Hardware Design Aid. In IEEE International Conference on Computer Design: VLSI in Computers and Processors, pages 522{525, 1992. [36] D. L. Dill, S. Park, and A. G. Nowatzyk. Formal Speci cation of Abstract Memory Models. In Research on Integrated Systems: Proceedings of the 1993 Symposium, MIT Press, pages 38{52, 1993. [37] M. Dubois, C. Scheurich, and F. Briggs. Memory Access Bu ering in Multiprocessors. In Proceedings of the 13th International Symposium on Computer Architecture, pages 434{442, June 1986. [38] S. Eggers and R. H. Katz. Evaluating the Performance for Four Snooping Cache Coherency Protocols. In Proceedings of the 16th International Symposium on Computer Architecture, May1989. [39] S. J. Eggers and R. H. Katz. A Characterization of Sharing in Parallel Programs and Its Application to Coherency Protocol Evaluation. In Proceedings of the 14th International Symposium on Computer Architecture, May 1987. [40] E. A. Emerson. Temporal and Modal Logic. In J. V. Leeuwen, editor, Handbook of Theoretical Computer Science, Volume B, Formal Models and Semantics. MIT Press, 1990. 172
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CSAIL Computer Science and Artifici
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Design and Veri cation of Adaptive
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I am truly grateful to my parents f
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4 The Base Cache Coherence Protocol
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List of Figures 1.1 Impact of Archi
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Chapter 1 Introduction Shared memor
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transparent and exposed only for lo
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Example 1: Can both registers r1 an
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and release locks, which guard ever
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that are interconnected with an o -
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although various techniques have be
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y showing that each processor can a
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s1 if p (s1) ! s2 where s1 and s2 a
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Program counter (pc) +1 Instruction
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Branch target buffer (btb) Program
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instruction is waiting to be dispat
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Current State: Proc(ia, rf , rob, b
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Rule Name mem pmb mpb Next mem Next
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Specification Implementation t 1 B
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Intuitively, \2P " means that \P is
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(a) (b) PC 1005 PC 2000 Instruction
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ewritten to s2 according to rule R.
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It can be shown that the relaxed di
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Chapter 3 The Commit-Reconcile & Fe
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Producer Storel(a,v) Commit(a) Cons
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Commit/Reconcile Purge Loadl/Commit
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instructions, because of the lack o
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CRF-Relaxed-Commit Rule Site(sache,
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3.4 Universality of the CRF Model M
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Translation from CRF to PSO: The Fe
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proc proc proc pmb mpb pmb mpb pmb
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Chapter 4 The Base Cache Coherence
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can be classi ed into two non-overl
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arbitrarily in an outgoing queue (t
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4.3 The Imperative Rules of the Bas
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Imperative Processor Rules Instruct
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Figure 4.5 de nes the rules of the
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4.5.2 Mapping from Base to CRF We d
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Base Imperative Rule CRF Rule IP1 (
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Base Rule Base Imperative Rule P1 I
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eceives a CacheReq message, it will
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e completed if it has an in nite nu
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SYS Sys(MSITE, SITEs) System MSITE
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Commit/Reconcile C-Receive-WbAck Ru
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message can be resumed eventually.
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If the memory state shows that the
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5.3.3 FIFO Message Passing The live
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Figure 5.7 gives the M-engine rules
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Backward-Message-Cache-to-Mem-for-W
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5.4.3 Simulation of WP in CRF Theor
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WP Imperative Rule CRF Rules IP1 (L
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WP Rule WP Imperative & Directive R
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(4) Msg(H,id ,Cache,a,-)" 2 Cin id(
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This completes the proof according
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emains as CachePending, there mustb
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M-engine Rules Msg from id Mstate A
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Chapter 6 The Migratory Cache Coher
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Commit/Reconcile Send Purge Loadl/C
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Mandatory Processor Rules Instructi
Page 123 and 124: while the memory sends a FlushReq m
Page 125 and 126: Lemma 38 D is strongly terminating
Page 127 and 128: Migratory Imperative Rule CRF Rules
Page 129 and 130: Cell(a,v,C[id ]) 2 Mem(s) _ Cell(a,
Page 131 and 132: According to Theorem-C and Lemma 45
Page 133 and 134: CacheReq message. In the latter cas
Page 135 and 136: Chapter 7 Cachet: A Seamless Integr
Page 137 and 138: 7.1.1 Putting Things Together It is
Page 139 and 140: Writeback Operations In Cachet, a w
Page 141 and 142: Composite Message Equivalent Sequen
Page 143 and 144: Imperative Processor Rules Instruct
Page 145 and 146: Invalid Commit/Reconcile Receive Ca
Page 147 and 148: Composite Imperative C-engine Rules
Page 149 and 150: 7.4 The Cachet Cache Coherence Prot
Page 151 and 152: Voluntary C-engine Rules Cstate Act
Page 153 and 154: The memory processes an incoming Ca
Page 155 and 156: The inaccuracy of memory states can
Page 157 and 158: C-engine Rule of Cachet Deriving Im
Page 159 and 160: Composite Mandatory Processor Rules
Page 161 and 162: memory regions simultaneously. In a
Page 163 and 164: Chapter 8 Conclusions This thesis h
Page 165 and 166: and heuristic policies. Mandatory r
Page 167 and 168: technique can be used to allow a ca
Page 169 and 170: Voluntary C-engine Rules Cstate Act
Page 171 and 172: FIFO Message Passing msg1 msg2 msg2
Page 173: [13] J. K. Archibald. The Cache Coh
Page 177 and 178: [71] J. Kuskin, D. Ofelt, M. Heinri
Page 179 and 180: [101] F. Pong and M. Dubois. A New
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