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Design and Verification of Adaptive Cache Coherence Protocols ...

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Base Rule Base Imperative Rule<br />

P1 IP1 (Loadl-on-Clean)<br />

P2 IP2 (Loadl-on-Dirty)<br />

P3<br />

P4<br />

P5 IC3 (C-Send-<strong>Cache</strong>Req)<br />

P6 IP3 (Storel-on-Clean)<br />

P7 IP4 (Storel-on-Dirty)<br />

P8<br />

P9<br />

P10 IC3 (C-Send-<strong>Cache</strong>Req)<br />

P11 IP5 (Commit-on-Clean)<br />

P12 IC2 (C-Send-Wb)<br />

P13<br />

P14<br />

P15 IP6 (Commit-on-Invalid)<br />

P16 IC1 (C-Purge)<br />

P17 IP7 (Reconcile-on-Dirty)<br />

P18<br />

P19<br />

P20 IP8 (Reconcile-on-Invalid)<br />

VC1 IC1 (C-Purge)<br />

VC2 IC2 (C-Send-Wb)<br />

VC3 IC3 (C-Send-<strong>Cache</strong>Req)<br />

MC1 IC4 (C-Receive-<strong>Cache</strong>)<br />

MC2 IC5 (C-Receive-WbAck)<br />

MM1 IM1 (M-Receive-<strong>Cache</strong>Req-&-Send-<strong>Cache</strong>)<br />

MM2 IM2 (M-Receive-Wb-&-Send-WbAck)<br />

Figure 4.7: Derivation <strong>of</strong> Base from Imperative Rules<br />

If Rule IM1 (M-Receive-<strong>Cache</strong>Req-&-Send-<strong>Cache</strong>) applies, then<br />

Cell(a,v) 2 Mem(s1) ^ Msg(id ,H,<strong>Cache</strong>Req,a) 2 Min(s1) ^<br />

Cell(a,v) 2 Mem(s2) ^ Msg(H,id ,<strong>Cache</strong>,a,v) 2 Mout(s2)<br />

) Cell(a,v) 2 Mem(dr(s1)) ^ a =2 <strong>Cache</strong> id(dr(s1)) ^ (Lemmas 5 & 8 )<br />

Cell(a,v) 2 Mem(dr(s2)) ^ Cell(a,v,Clean) 2 <strong>Cache</strong> id(dr(s2)) (Lemmas 5 & 8 )<br />

) f(s1) ! f(s2) (CRF-<strong>Cache</strong> )<br />

If Rule IM2 (M-Receive-Wb-&-Send-WbAck) applies, then<br />

Msg(id ,H,Wb,a,v) 2 Min(s1) ^<br />

Cell(a,v) 2 Mem(s2) ^ Msg(H,id ,WbAck,a) 2 Mout(s2)<br />

) Cell(a,v,Dirty) 2 <strong>Cache</strong> id(dr(s1)) ^ (Lemma 8 )<br />

Cell(a,v) 2 Mem(dr(s2)) ^ Cell(a,v,Clean) 2 <strong>Cache</strong> id(dr(s2)) (Lemmas 5 & 8 )<br />

) f(s1) ! f(s2) (CRF-Writeback )<br />

Draining Rules<br />

If Rule IC2 (C-Send-Wb), IC3 (C-Send-<strong>Cache</strong>Req), IC4 (C-Receive-<strong>Cache</strong>), IC5 (C-Receive-<br />

WbAck), Message-<strong>Cache</strong>-to-Mem or Message-Mem-to-<strong>Cache</strong> applies, then<br />

f(s1) =f(s2) (Since the rule or its backward version is a draining rule)<br />

Figure 4.6 summarizes the simulation pro<strong>of</strong>. 2<br />

81

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