Design and Verification of Adaptive Cache Coherence Protocols ...

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(Rule MM32). The memory can choose to acknowledge the last writeback with a WbAckw message to allow the cache to retain a WP copy (Rule MM33). The memory processes an incoming Downwb, Downmw or DownVmw message as follows: When the memory receives a Downwb message, if the memory state shows that the cache contains a WP copy for the address, the memory removes the cache identi er from the corresponding directory (Rules MM21 and MM22). If the memory state shows that the cache contains a Migratory copy for the address, the memory updates the memory state to indicate that the address is no longer cached in any cache (Rules MM23, MM24 and MM25). This can happen because the memory can voluntarily send an upgrade message to upgrade a cache cell from WP to Migratory, while the cache has downgraded the cache cell from WP to Base. The downgrade operation has higher priority than the upgrade operation. When the memory receivesaDownmw message, it sets the memory state to indicate that the cache contains a WP copy for the address (Rules MM26, MM27 and MM28). When the memory receives a DownVmw message, it updates the memory value and sets the memory state to indicate that the cache contains a WP copy for the address (Rules MM29, MM30 and MM31). In addition, the Tw[ , ] state can be converted to C[ ]. This is necessary to ensure that a transient memory state will become a stable memory state eventually so that stalled cache requests can be serviced. Voluntary Rules There are ve voluntary rules that allow the memory to supply a cache copy to a cache, to upgrade a cache cell or to downgrade a cache cell. If the memory state is Cw[dir], the memory can send a Cachew message to supply a WP copy to cache site id , where id =2 dir. If the memory state is Cw[id ], the memory can send an Upwm message to cache site id to upgrade the cache cell from WP to Migratory. If the memory state is Cw[dir], the memory can multicast a DownReqwb message to cache sites dir to downgrade the cache cells from WP to Base. If the memory state is Cm[id ], the memory can send a DownReqmw message to cache site id to downgrade the cache cell from Migratory to WP. If the memory state is T 0 m[id ], the memory can send a DownReqwb message to cache site id to downgrade the cache cell from WP to Base. The memory state can be imprecise since it maintains no information about the existence of Base cells. In addition, when the memory state shows that a cache contains a WP or Migratory cell for an address, it is possible that the cache cell has already been downgraded. 152
The inaccuracy of memory states can cause unexpected cases that must be dealt with properly. Some scenarios are discussed as follows: Simultaneous Cachew and Wbb. Suppose initially the address is cached in the Dirty state of Base in a cache, while the memory state shows that the address is uncached in the cache. The memory sends a Cachew message to supply a WP copy to the cache, while the cache sends a Wbb message to write the dirty copyback to the memory. The Cachew message will be discarded when it is received (Rule MC4). Simultaneous Upwm and Downmw. Suppose initially the address is cached in the Clean or Dirty state of WP, while the memory state shows that the address is exclusively cached under WP in the cache. The memory sends an Upwm message to upgrade the cache cell from WP to Migratory, while the cache downgrades the cell from WP to Base and sends a Downwb message to the memory. The Upwm message will be discarded when it is received (Rules MC7 and MC8). Simultaneous DownReqwb and Downwb. Suppose initially the address is cached in the Clean or Dirty state of WP. The memory sends a DownReqwb message to the cache, while the cache downgrades the cell from WP to Base before it receives the request. The DownReqwb message will be discarded when it is received (Rules MC16 and MC17). Bu er Management When a cache request is stalled, it should not block other messages in the incoming queue from being processed. This can be achieved via proper bu er management to allow an incoming message to overtake acache request as long as the two messages are from di erent cache sites or have di erent addresses. This can be characterized as follows: Cachet's bu er management: msg1 msg2 msg2 msg1 if (Cmd(msg1)=CacheReq _ Cmd(msg2)=CacheReq) ^ (Src(msg1) 6=Src(msg2) _ Addr(msg1) 6=Addr(msg2)) 7.4.4 Derivation of Cachet from Imperative and Directive Rules The Cachet rules can be derived from the imperative and directive rules. A directive rule can be used to generate or discard a directive message it cannot modify any system state that may a ect the soundness of the system. There are four basic directive rules that involve the basic directive messages. Send-DownReqwb: The memory sends a DownReqwb message to a cache. Send-DownReqmw: The memory sends a DownReqmw message to a cache. Receive-DownReqwb: The cache discards an incoming DownReqwb message. Receive-DownReqmw: The cache discards an incoming DownReqmw message. 153
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CSAIL Computer Science and Artifici
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Design and Veri cation of Adaptive
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I am truly grateful to my parents f
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4 The Base Cache Coherence Protocol
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List of Figures 1.1 Impact of Archi
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Chapter 1 Introduction Shared memor
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transparent and exposed only for lo
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Example 1: Can both registers r1 an
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and release locks, which guard ever
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that are interconnected with an o -
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although various techniques have be
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y showing that each processor can a
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s1 if p (s1) ! s2 where s1 and s2 a
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Program counter (pc) +1 Instruction
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Branch target buffer (btb) Program
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instruction is waiting to be dispat
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Current State: Proc(ia, rf , rob, b
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Rule Name mem pmb mpb Next mem Next
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Specification Implementation t 1 B
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Intuitively, \2P " means that \P is
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(a) (b) PC 1005 PC 2000 Instruction
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ewritten to s2 according to rule R.
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It can be shown that the relaxed di
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Chapter 3 The Commit-Reconcile & Fe
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Producer Storel(a,v) Commit(a) Cons
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Commit/Reconcile Purge Loadl/Commit
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instructions, because of the lack o
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CRF-Relaxed-Commit Rule Site(sache,
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3.4 Universality of the CRF Model M
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Translation from CRF to PSO: The Fe
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proc proc proc pmb mpb pmb mpb pmb
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Chapter 4 The Base Cache Coherence
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can be classi ed into two non-overl
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arbitrarily in an outgoing queue (t
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4.3 The Imperative Rules of the Bas
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Imperative Processor Rules Instruct
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Figure 4.5 de nes the rules of the
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4.5.2 Mapping from Base to CRF We d
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Base Imperative Rule CRF Rule IP1 (
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Base Rule Base Imperative Rule P1 I
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eceives a CacheReq message, it will
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e completed if it has an in nite nu
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SYS Sys(MSITE, SITEs) System MSITE
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Commit/Reconcile C-Receive-WbAck Ru
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message can be resumed eventually.
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If the memory state shows that the
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5.3.3 FIFO Message Passing The live
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Figure 5.7 gives the M-engine rules
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Backward-Message-Cache-to-Mem-for-W
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Page 107 and 108: WP Rule WP Imperative & Directive R
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Page 111 and 112: This completes the proof according
Page 113 and 114: emains as CachePending, there mustb
Page 115 and 116: M-engine Rules Msg from id Mstate A
Page 117 and 118: Chapter 6 The Migratory Cache Coher
Page 119 and 120: Commit/Reconcile Send Purge Loadl/C
Page 121 and 122: Mandatory Processor Rules Instructi
Page 123 and 124: while the memory sends a FlushReq m
Page 125 and 126: Lemma 38 D is strongly terminating
Page 127 and 128: Migratory Imperative Rule CRF Rules
Page 129 and 130: Cell(a,v,C[id ]) 2 Mem(s) _ Cell(a,
Page 131 and 132: According to Theorem-C and Lemma 45
Page 133 and 134: CacheReq message. In the latter cas
Page 135 and 136: Chapter 7 Cachet: A Seamless Integr
Page 137 and 138: 7.1.1 Putting Things Together It is
Page 139 and 140: Writeback Operations In Cachet, a w
Page 141 and 142: Composite Message Equivalent Sequen
Page 143 and 144: Imperative Processor Rules Instruct
Page 145 and 146: Invalid Commit/Reconcile Receive Ca
Page 147 and 148: Composite Imperative C-engine Rules
Page 149 and 150: 7.4 The Cachet Cache Coherence Prot
Page 151 and 152: Voluntary C-engine Rules Cstate Act
Page 153: The memory processes an incoming Ca
Page 157 and 158: C-engine Rule of Cachet Deriving Im
Page 159 and 160: Composite Mandatory Processor Rules
Page 161 and 162: memory regions simultaneously. In a
Page 163 and 164: Chapter 8 Conclusions This thesis h
Page 165 and 166: and heuristic policies. Mandatory r
Page 167 and 168: technique can be used to allow a ca
Page 169 and 170: Voluntary C-engine Rules Cstate Act
Page 171 and 172: FIFO Message Passing msg1 msg2 msg2
Page 173 and 174: [13] J. K. Archibald. The Cache Coh
Page 175 and 176: [41] A. Erlichson, N. Nuckolls, G.
Page 177 and 178: [71] J. Kuskin, D. Ofelt, M. Heinri
Page 179 and 180: [101] F. Pong and M. Dubois. A New
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