Design and Verification of Adaptive Cache Coherence Protocols ...

5.4.4 Soundness of WP
The WP protocol de ned in Figure 5.5 consists of integrated rules that can be derived from
the imperative and directive rules of WP. The imperative rules are given in Section 5.2. In
the remainder of this section, we give the directive rules and show the derivation of WP rules.
A directive rule involves generating or discarding a directive message, which can be used to
specify conditions under which an imperative action should be invoked.
C-Send-CacheReq Rule
Site(id , cache, in, out, pmb, mpb, proc)
! Site(id , cache, in, out Msg(id ,H,CacheReq,a), pmb, mpb, proc)
C-Receive-PurgeReq Rule
Site(id , cache, Msg(H,id ,PurgeReq,a) in, out, pmb, mpb, proc)
! Site(id , cache, in, out, pmb, mpb, proc)
M-Send-PurgeReq Rule
Msite(mem, in, out)
! Msite(mem, in, out Msg(H,id ,PurgeReq,a))
M-Receive-CacheReq Rule
Msite(mem, Msg(id ,H,CacheReq,a) in, out)
! Msite(mem, in, out)
Figure 5.9 gives the imperative and directive rules used in the derivation for each WP rule (a
rule marked with ` 'may be applied zero or many times). In the derivation, the CachePending
state used in the integrated rules is mapped to the Invalid state of the imperative rules, and
the C[dir] state used in the integrated rules is mapped to the T[dir, ] state of the imperative
rules. For example, consider Rule MM5 that deals with an incoming writeback message. It
involves applying the imperative M-Receive-Wb rule to suspend the writeback message, and
the directive M-Send-PurgeReq rule to generate purge requests.
A directive rule by itself cannot modify any system state that may a ect soundness. There-
fore, it su ces to verify the soundness of the protocol with respect to the imperative rules, rather
than the integrated rules. This can dramatically simplify the veri cation since the number of
imperative rules is much smaller than the number of integrated rules.
5.5 Liveness Proof of the WP Protocol
In this section, we prove the liveness of WP by showing that an instruction can always be
completed so that each processor can make progress. That is, whenever a processor intends to
execute a memory instruction, the cache cell will be brought to an appropriate state so that the
instruction can be retired. The lemmas and theorems in this section are given in the context of
the integrated rules of WP, which involve both imperative and directive messages. We assume
FIFO message passing and proper bu er management as described in Section 5.3.
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