Design and Verification of Adaptive Cache Coherence Protocols ...

SYS Sys(MSITE, SITEs) System
MSITE Msite(MEM, IN, OUT) Memory Site
MEM [] Cell(a,v,MSTATE) j MEM Memory
SITEs SITE [] SITE j SITEs Set of Cache Sites
SITE Site(id , CACHE, IN, OUT, PMB, MPB, PROC) Cache Site
CACHE [] Cell(a,v,CSTATE) j CACHE Cache
IN [] MSG IN Incoming Queue
OUT [] MSG OUT Outgoing Queue
MSG Msg(src,dest,CMD,a,v) Message
MSTATE C[ ] [] C[id ] [] T[id ] Memory state
CSTATE Clean [] Dirty [] CachePending Cache State
CMD Cache [] Purge [] Flush []
CacheReq [] FlushReq Command
Figure 6.1: System Con guration of Migratory
Purge: the cache informs the memory that its cache copy has been purged.
Flush: the cache sends the dirty databack to the memory.
CacheReq: the cache requests a data copy from the memory.
6.2 The Imperative Rules of the Migratory Protocol
We develop a set of imperative rules that determine the soundness of the system. The imperative
rules include the processor rules, the cache engine rules and the memory engine rules.
Processor Rules: The imperative processor rules of Migratory contain all the imperative
processor rules of Base (see Section 4.3). In addition, the Commit-on-Dirty rule allows a
Commit instruction to complete even when the address is cached in the Dirty state, and the
Reconcile-on-Clean rule allows a Reconcile instruction to complete even when the address is
cached in the Clean state.
Commit-on-Dirty Rule
Site(id , Cell(a,v,Dirty) j cache, in, out, ht,Commit(a)ipmb, mpb, proc)
! Site(id , Cell(a,v,Dirty) j cache, in, out, pmb, mpbjht,Acki, proc)
Reconcile-on-Clean Rule
Site(id , Cell(a,v,Clean) j cache, in, out, ht,Reconcile(a)ipmb, mpb, proc)
! Site(id , Cell(a,v,Clean) j cache, in, out, pmb, mpbjht,Acki, proc)
C-engine Rules: Acache can purge a clean copy and inform the memory via a Purge mes-
sage. It can also ush a dirty copy and write the data back to the memory via a Flush message.
It is worth noting that no acknowledgment is needed from the memory for the ush operation.
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