Design and Verification of Adaptive Cache Coherence Protocols ...

INST Loadl(a) [] Storel(a,v)
[] Commit(a) [] Reconcile(a)
[] Fencerr(a1,a2) [] Fencerw(a1,a2)
[] Fencewr(a1,a2) [] Fenceww(a1,a2)
Figure 3.1: CRF Instructions
proc proc proc
pmb mpb pmb mpb pmb mpb
sache sache sache
memory
SYS Sys(MEM, SITEs) System
SITEs SITE [] SITE j SITEs Set of Sites
SITE Site(SACHE, PMB, MPB, PROC) Site
SACHE [] Cell(a,v,CSTATE) j SACHE Semantic Cache
CSTATE Clean [] Dirty Cache State
PMB [] ht,INSTiPMB Processor-to-Memory Bu er
MPB [] ht,REPLYijMPB Memory-to-Processor Bu er
REPLY v [] Ack Reply
Figure 3.2: System Con guration of CRF
produced by one processor can be observed by another processor whenever necessary. CRF
allows memory accesses to be reordered as long as data dependence constraints are preserved.
The de nition of CRF includes two sets of rules. The rst set of rules speci es the execution
of Loadl, Storel, Commit and Reconcile instructions. It also includes rules that govern the
data propagation between semantic caches and memory. The second set of rules deals with
instruction reordering and memory fences. We also refer to the rst set of rules as the Commit-
Reconcile (CR) model, because these rules by themselves de ne a memory model which isthe
same as CRF except that instructions are executed strictly in-order.
3.1.1 The CR Model
There are two states for sache cells, Clean and Dirty. The Clean state indicates that the data
has not been modi ed since it was cached or last written back. The Dirty state indicates that
the data has been modi ed and has not been written back to the memory since then. Note in
CRF, di erent saches can have a cell with the same address but di erent values.
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