Design and Verification of Adaptive Cache Coherence Protocols ...

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Commit/Reconcile Invalid Send Purge Send CacheReq Cache- Receive Cache Pending Receive Cache Loadl/Commit/Reconcile Clean Storel Send Flush Figure 6.5: Cache State Transitions of Migratory Loadl/Storel/Commit/Reconcile ensures that a cache request cannot be blocked forever while cache requests from other sites are serviced repeatedly. The Migratory protocol assumes proper bu er management that can be characterized as follows: Migratory's bu er management: msg1 msg2 msg2 msg1 if (Cmd(msg1)=CacheReq _ Cmd(msg2)=CacheReq) ^ (Src(msg1) 6=Src(msg2) _ Addr(msg1) 6=Addr(msg2)) Voluntary Rules: At any time, a cache can purge a clean copy and notify the memory of the purge operation via a Purge message. It can also ush a dirty copy and write the data back to the memory via a Flush message. Acache can send a cache request to the memory to request an exclusive copy for an uncached address. Figure 6.5 shows the cache state transitions of Migratory. On the other hand, the memory can voluntarily send an exclusive copy to a cache, if the address is currently not cached in any cache. If the memory state shows that an address is cached in some cache, the memory can voluntarily send a ush request to the cache to force the data to be ushed from the cache. The voluntary rules allow the memory to supply a data copy without a request from the cache, and a cache to ush a data copy without a request from the memory. This can cause unexpected Dirty situations if a request is received after the requested action has been performed. Simultaneous Cache and CacheReq. Suppose initially the address is not cached in any cache. The memory sends a Cache message to a cache, while the cache sends a CacheReq to the memory. The CacheReq message will be discarded when it is received at the memory (Rules MM3 & MM5). Simultaneous Purge and FlushReq. Suppose initially a clean copy of the address is cached in a cache site. The cache purges the clean copy and sends a Purge message to the memory, while the memory sends a FlushReq message to the cache. The FlushReq message will be discarded when it received at the cache (Rules MC5 and MC6). Simultaneous Flush and FlushReq. Suppose initially a dirty copy of the address is cached in a cache site. The cache ushes the dirtycopy and sends a Flush message to the memory, 120
while the memory sends a FlushReq message to the cache. The FlushReq message will be discarded when it received at the cache (Rules MC5 and MC6). Optimizations: In Migratory, an instruction is always stalled when the address is cached in a transient state. A potential optimization is to allow a Commit or Reconcile instruction to be completed regardless of the current cache state. This cannot compromise the soundness of the protocol, since no distinction is drawn between CachePending and Invalid in terms of soundness. FIFO Message Passing: The liveness of Migratory is contingent uponFIFO message passing. Consider a scenario in which a cache sends a Flush message to write a data copy backto the memory, followed by a CacheReq message to request a data copy from the memory. The CacheReq message would be discarded if it were received before the Flush message, which could lead to a deadlock or livelock situation. The Migratory protocol requires that FIFO ordering be maintained in the following cases: Cache followed by FlushReq. The memory sends a Cache message to a cache to supply a data copy, and then sends a FlushReq message to ush the copy. Purge or Flush followed by CacheReq. A cache sends a Purge or Flush message to the memory, and then sends a CacheReq message to request a data copy from the memory. It is worth mentioning that there are also cases that require no FIFO message passing although multiple messages regarding the same address are involved. This happens when the preceding message is a directive message. CacheReq followed by Purge. Acache sends a CacheReq message to the memory. Before the CacheReq message is received, the memory voluntarily sends a Cache message to the cache. The cache receives the Cache message and caches the data in the Clean state. The cache then purges the clean copy and sends a Purge message to the memory. The CacheReq message and the Purge message can be reordered. CacheReq followed by Flush. Acache sends a CacheReq message to the memory. Before the CacheReq message is received, the memory voluntarily sends a Cache message to the cache. The cache receives the Cache message and caches the data in the Clean state. The processor performs a Storel instruction, and the cache state becomes Dirty. The cache then ushes the dirty copy and sends a Flush message to the memory. The CacheReq message and the Flush message can be reordered. FlushReq followed by Cache. The memory sends a FlushReq message to the cache where the address is cached. Before the FlushReq message is received, the cache voluntarily ushes the cache copy and sends a Purge or Flush message to the memory. The memory receives the message, and then sends a Cache message to the cache. The FlushReq message and the Cache message can be reordered. 121
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CSAIL Computer Science and Artifici
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Design and Veri cation of Adaptive
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I am truly grateful to my parents f
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4 The Base Cache Coherence Protocol
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List of Figures 1.1 Impact of Archi
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Chapter 1 Introduction Shared memor
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transparent and exposed only for lo
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Example 1: Can both registers r1 an
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and release locks, which guard ever
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that are interconnected with an o -
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although various techniques have be
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y showing that each processor can a
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s1 if p (s1) ! s2 where s1 and s2 a
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Program counter (pc) +1 Instruction
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Branch target buffer (btb) Program
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instruction is waiting to be dispat
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Current State: Proc(ia, rf , rob, b
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Rule Name mem pmb mpb Next mem Next
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Specification Implementation t 1 B
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Intuitively, \2P " means that \P is
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(a) (b) PC 1005 PC 2000 Instruction
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ewritten to s2 according to rule R.
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It can be shown that the relaxed di
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Chapter 3 The Commit-Reconcile & Fe
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Producer Storel(a,v) Commit(a) Cons
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Commit/Reconcile Purge Loadl/Commit
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instructions, because of the lack o
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CRF-Relaxed-Commit Rule Site(sache,
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3.4 Universality of the CRF Model M
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Translation from CRF to PSO: The Fe
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proc proc proc pmb mpb pmb mpb pmb
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Chapter 4 The Base Cache Coherence
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can be classi ed into two non-overl
Page 71 and 72: arbitrarily in an outgoing queue (t
Page 73 and 74: 4.3 The Imperative Rules of the Bas
Page 75 and 76: Imperative Processor Rules Instruct
Page 77 and 78: Figure 4.5 de nes the rules of the
Page 79 and 80: 4.5.2 Mapping from Base to CRF We d
Page 81 and 82: Base Imperative Rule CRF Rule IP1 (
Page 83 and 84: Base Rule Base Imperative Rule P1 I
Page 85 and 86: eceives a CacheReq message, it will
Page 87 and 88: e completed if it has an in nite nu
Page 89 and 90: SYS Sys(MSITE, SITEs) System MSITE
Page 91 and 92: Commit/Reconcile C-Receive-WbAck Ru
Page 93 and 94: message can be resumed eventually.
Page 95 and 96: If the memory state shows that the
Page 97 and 98: 5.3.3 FIFO Message Passing The live
Page 99 and 100: Figure 5.7 gives the M-engine rules
Page 101 and 102: Backward-Message-Cache-to-Mem-for-W
Page 103 and 104: 5.4.3 Simulation of WP in CRF Theor
Page 105 and 106: WP Imperative Rule CRF Rules IP1 (L
Page 107 and 108: WP Rule WP Imperative & Directive R
Page 109 and 110: (4) Msg(H,id ,Cache,a,-)" 2 Cin id(
Page 111 and 112: This completes the proof according
Page 113 and 114: emains as CachePending, there mustb
Page 115 and 116: M-engine Rules Msg from id Mstate A
Page 117 and 118: Chapter 6 The Migratory Cache Coher
Page 119 and 120: Commit/Reconcile Send Purge Loadl/C
Page 121: Mandatory Processor Rules Instructi
Page 125 and 126: Lemma 38 D is strongly terminating
Page 127 and 128: Migratory Imperative Rule CRF Rules
Page 129 and 130: Cell(a,v,C[id ]) 2 Mem(s) _ Cell(a,
Page 131 and 132: According to Theorem-C and Lemma 45
Page 133 and 134: CacheReq message. In the latter cas
Page 135 and 136: Chapter 7 Cachet: A Seamless Integr
Page 137 and 138: 7.1.1 Putting Things Together It is
Page 139 and 140: Writeback Operations In Cachet, a w
Page 141 and 142: Composite Message Equivalent Sequen
Page 143 and 144: Imperative Processor Rules Instruct
Page 145 and 146: Invalid Commit/Reconcile Receive Ca
Page 147 and 148: Composite Imperative C-engine Rules
Page 149 and 150: 7.4 The Cachet Cache Coherence Prot
Page 151 and 152: Voluntary C-engine Rules Cstate Act
Page 153 and 154: The memory processes an incoming Ca
Page 155 and 156: The inaccuracy of memory states can
Page 157 and 158: C-engine Rule of Cachet Deriving Im
Page 159 and 160: Composite Mandatory Processor Rules
Page 161 and 162: memory regions simultaneously. In a
Page 163 and 164: Chapter 8 Conclusions This thesis h
Page 165 and 166: and heuristic policies. Mandatory r
Page 167 and 168: technique can be used to allow a ca
Page 169 and 170: Voluntary C-engine Rules Cstate Act
Page 171 and 172: FIFO Message Passing msg1 msg2 msg2
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[13] J. K. Archibald. The Cache Coh
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[41] A. Erlichson, N. Nuckolls, G.
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[71] J. Kuskin, D. Ofelt, M. Heinri
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[101] F. Pong and M. Dubois. A New
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