Design and Verification of Adaptive Cache Coherence Protocols ...

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Imperative Processor Rules Instruction Cstate Action Next Cstate Loadl(a) Cell(a,v,Clean) retire Cell(a,v,Clean) IP1 Cell(a,v,Dirty) retire Cell(a,v,Dirty) IP2 Storel(a,v) Cell(a,-,Clean) retire Cell(a,v,Dirty) IP3 Cell(a,-,Dirty) retire Cell(a,v,Dirty) IP4 Commit(a) Cell(a,v,Clean) retire Cell(a,v,Clean) IP5 Cell(a,v,Dirty) retire Cell(a,v,Dirty) IP6 a =2 cache retire a =2 cache IP7 Reconcile(a) Cell(a,v,Clean) retire Cell(a,v,Clean) IP8 Cell(a,v,Dirty) retire Cell(a,v,Dirty) IP9 a =2 cache retire a =2 cache IP10 Imperative C-engine Rules Msg from H Cstate Action Next Cstate Cell(a,-,Clean) hPurge,ai!H a =2 cache IC1 Cell(a,v,Dirty) hFlush,a,vi!H a =2 cache IC2 hCache,a,vi a =2 cache Cell(a,v,Clean) IC3 Imperative M-engine Rules Msg from id Mstate Action Next Mstate Cell(a,v,C[ ]) hCache,a,vi!id Cell(a,v,C[id ]) IM1 hPurge,ai Cell(a,v,C[id ]) Cell(a,v,C[ ]) IM2 hFlush,a,vi Cell(a,-,C[id ]) Cell(a,v,C[ ]) IM3 6.3 The Migratory Protocol Figure 6.3: Imperative Rules of Migratory To ensure liveness, we introduce two directive messages, CacheReq and FlushReq. Whenever necessary, a cache can send a CacheReq message to request a data copy from the memory, and the memory can send a FlushReq message to force a cache copy to be ushed. In addition, we augment certain cache and memory states with information regarding outstanding directive messages. The Invalid cache state in the imperative rules becomes Invalid or CachePending, depending on whether a cache request has been sent to the memory. At the memory side, the C[id ] state in the imperative rules becomes C[id ] or T[id ], depending on whether a ush request has been sent to the cache site. Figure 6.4 gives the rules of the Migratory protocol. The tabular description can be easily translated into formal TRS rules. A mandatory rule marked with `SF' requires strong fairness to ensure that each memory instruction can be retired eventually. A retired instruction is immediately removed from the processor-to-memory bu er, while a stalled instruction remains for later processing. When a message is processed, it is removed from the incoming queue when a message is stalled, it remains in the incoming queue but does not block following messages. The Migratory protocol assumes FIFO message passing for protocol messages with the same address. For each address, the memory maintains which site currently has cached the address. When it receives a cache request while the address is cached in another cache, it stalls the cache request and sends a ush request to the cache to force it to ush its copy. Note that there can be multiple stalled cache requests regarding the same address. The strong fairness of Rule MM1 118
Mandatory Processor Rules Instruction Cstate Action Next Cstate Loadl(a) Cell(a,v,Clean) retire Cell(a,v,Clean) P1 SF Cell(a,v,Dirty) retire Cell(a,v,Dirty) P2 SF Cell(a,-,CachePending) stall Cell(a,-,CachePending) P3 a =2 cache stall, hCacheReq,ai !H Cell(a,-,CachePending) P4 Storel(a,v) Cell(a,-,Clean) retire Cell(a,v,Dirty) P5 SF Cell(a,-,Dirty) retire Cell(a,v,Dirty) P6 SF Cell(a,-,CachePending) stall Cell(a,-,CachePending) P7 a =2 cache stall, hCacheReq,ai !H Cell(a,-,CachePending) P8 Commit(a) Cell(a,v,Clean) retire Cell(a,v,Clean) P9 SF Cell(a,v,Dirty) retire Cell(a,v,Dirty) P10 SF Cell(a,-,CachePending) stall Cell(a,-,CachePending) P11 a =2 cache retire a =2 cache P12 SF Reconcile(a) Cell(a,v,Clean) retire Cell(a,v,Clean) P13 SF Cell(a,v,Dirty) retire Cell(a,v,Dirty) P14 SF Cell(a,-,CachePending) stall Cell(a,-,CachePending) P15 a =2 cache retire a =2 cache P16 SF Voluntary C-engine Rules Cstate Action Next Cstate Cell(a,-,Clean) hPurge,ai!H a =2 cache VC1 Cell(a,v,Dirty) hFlush,a,vi!H a =2 cache VC2 a =2 cache hCacheReq,ai !H Cell(a,-,CachePending) VC3 Mandatory C-engine Rules Msg from H Cstate Action Next Cstate hCache,a,vi a =2 cache Cell(a,v,Clean) MC1 Cell(a,-,CachePending) Cell(a,v,Clean) MC2 hFlushReq,ai Cell(a,-,Clean) hPurge,ai!H a =2 cache MC3 Cell(a,v,Dirty) hFlush,a,vi!H a =2 cache MC4 Cell(a,-,CachePending) Cell(a,-,CachePending) MC5 a =2 cache a =2 cache MC6 Voluntary M-engine Rules Mstate Action Next Mstate Cell(a,v,C[ ]) hCache,a,vi !id Cell(a,v,C[id ]) VM1 Cell(a,v,C[id ]) hFlushReq,ai!id Cell(a,v,T[id ]) VM2 Mandatory M-engine Rules Msg from id Mstate Action Next Mstate hCacheReq,ai Cell(a,v,C[ ]) hCache,a,vi !id Cell(a,v,C[id ]) MM1 SF Cell(a,v,C[id1]) (id1 6= id ) stall message Cell(a,v,T[id1]) MM2 hFlushReq,ai!id1 Cell(a,v,C[id ]) Cell(a,v,C[id ]) MM3 Cell(a,-,T[id1]) (id1 6= id ) stall message Cell(a,-,T[id1]) MM4 Cell(a,-,T[id ]) Cell(a,-,T[id ]) MM5 hPurge,ai Cell(a,v,C[id ]) Cell(a,v,C[ ]) MM6 Cell(a,v,T[id ]) Cell(a,v,C[ ]) MM7 hFlush,a,vi Cell(a,-,C[id ]) Cell(a,v,C[ ]) MM8 Cell(a,-,T[id ]) Cell(a,v,C[ ]) MM9 Figure 6.4: The Migratory Protocol 119
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CSAIL Computer Science and Artifici
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Design and Veri cation of Adaptive
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I am truly grateful to my parents f
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4 The Base Cache Coherence Protocol
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List of Figures 1.1 Impact of Archi
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Chapter 1 Introduction Shared memor
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transparent and exposed only for lo
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Example 1: Can both registers r1 an
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and release locks, which guard ever
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that are interconnected with an o -
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although various techniques have be
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y showing that each processor can a
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s1 if p (s1) ! s2 where s1 and s2 a
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Program counter (pc) +1 Instruction
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Branch target buffer (btb) Program
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instruction is waiting to be dispat
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Current State: Proc(ia, rf , rob, b
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Rule Name mem pmb mpb Next mem Next
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Specification Implementation t 1 B
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Intuitively, \2P " means that \P is
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(a) (b) PC 1005 PC 2000 Instruction
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ewritten to s2 according to rule R.
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It can be shown that the relaxed di
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Chapter 3 The Commit-Reconcile & Fe
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Producer Storel(a,v) Commit(a) Cons
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Commit/Reconcile Purge Loadl/Commit
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instructions, because of the lack o
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CRF-Relaxed-Commit Rule Site(sache,
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3.4 Universality of the CRF Model M
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Translation from CRF to PSO: The Fe
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proc proc proc pmb mpb pmb mpb pmb
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Chapter 4 The Base Cache Coherence
Page 69 and 70: can be classi ed into two non-overl
Page 71 and 72: arbitrarily in an outgoing queue (t
Page 73 and 74: 4.3 The Imperative Rules of the Bas
Page 75 and 76: Imperative Processor Rules Instruct
Page 77 and 78: Figure 4.5 de nes the rules of the
Page 79 and 80: 4.5.2 Mapping from Base to CRF We d
Page 81 and 82: Base Imperative Rule CRF Rule IP1 (
Page 83 and 84: Base Rule Base Imperative Rule P1 I
Page 85 and 86: eceives a CacheReq message, it will
Page 87 and 88: e completed if it has an in nite nu
Page 89 and 90: SYS Sys(MSITE, SITEs) System MSITE
Page 91 and 92: Commit/Reconcile C-Receive-WbAck Ru
Page 93 and 94: message can be resumed eventually.
Page 95 and 96: If the memory state shows that the
Page 97 and 98: 5.3.3 FIFO Message Passing The live
Page 99 and 100: Figure 5.7 gives the M-engine rules
Page 101 and 102: Backward-Message-Cache-to-Mem-for-W
Page 103 and 104: 5.4.3 Simulation of WP in CRF Theor
Page 105 and 106: WP Imperative Rule CRF Rules IP1 (L
Page 107 and 108: WP Rule WP Imperative & Directive R
Page 109 and 110: (4) Msg(H,id ,Cache,a,-)" 2 Cin id(
Page 111 and 112: This completes the proof according
Page 113 and 114: emains as CachePending, there mustb
Page 115 and 116: M-engine Rules Msg from id Mstate A
Page 117 and 118: Chapter 6 The Migratory Cache Coher
Page 119: Commit/Reconcile Send Purge Loadl/C
Page 123 and 124: while the memory sends a FlushReq m
Page 125 and 126: Lemma 38 D is strongly terminating
Page 127 and 128: Migratory Imperative Rule CRF Rules
Page 129 and 130: Cell(a,v,C[id ]) 2 Mem(s) _ Cell(a,
Page 131 and 132: According to Theorem-C and Lemma 45
Page 133 and 134: CacheReq message. In the latter cas
Page 135 and 136: Chapter 7 Cachet: A Seamless Integr
Page 137 and 138: 7.1.1 Putting Things Together It is
Page 139 and 140: Writeback Operations In Cachet, a w
Page 141 and 142: Composite Message Equivalent Sequen
Page 143 and 144: Imperative Processor Rules Instruct
Page 145 and 146: Invalid Commit/Reconcile Receive Ca
Page 147 and 148: Composite Imperative C-engine Rules
Page 149 and 150: 7.4 The Cachet Cache Coherence Prot
Page 151 and 152: Voluntary C-engine Rules Cstate Act
Page 153 and 154: The memory processes an incoming Ca
Page 155 and 156: The inaccuracy of memory states can
Page 157 and 158: C-engine Rule of Cachet Deriving Im
Page 159 and 160: Composite Mandatory Processor Rules
Page 161 and 162: memory regions simultaneously. In a
Page 163 and 164: Chapter 8 Conclusions This thesis h
Page 165 and 166: and heuristic policies. Mandatory r
Page 167 and 168: technique can be used to allow a ca
Page 169 and 170: Voluntary C-engine Rules Cstate Act
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FIFO Message Passing msg1 msg2 msg2
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[13] J. K. Archibald. The Cache Coh
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[41] A. Erlichson, N. Nuckolls, G.
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[71] J. Kuskin, D. Ofelt, M. Heinri
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[101] F. Pong and M. Dubois. A New
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