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Current State: Proc(ia, rf , rob, btb, im) Rule Name Instruction at ia New Template in rob Next pc Fetch-Loadc r:=Loadc(v) Itb(ia,t :=v,Wr(r)) ia+1 Fetch-Loadpc r:=Loadpc Itb(ia,t :=ia,Wr(r)) ia+1 Fetch-Op r:=Op(r1,r2) Itb(ia,t :=Op(tv1,tv2),Wr(r)) ia+1 Fetch-Jz Jz(r1,r2) Itb(ia,Jz(tv1,tv2),Sp(btb[ia])) btb[ia] Fetch-Load r:=Load(r1) Itb(ia,t :=Load(tv1,U),Wr(r)) ia+1 Fetch-Store Store(r1,r2) Itb(ia,t :=Store(tv1,tv2,U)) ia+1 Figure 2.5: PS Instruction Fetch Rules Fetch-Op Rule Proc(ia, rf , rob, btb, im) if im[ia] = r:=Op(r1,r2) ! Proc(ia+1, rf , rob Itb(ia,t :=Op(tv1,tv2),Wr(r)), btb, im) Fetch-Jz Rule Proc(ia, rf , rob, btb, im) if im[ia] = Jz(r1,r2) ! Proc(pia, rf , rob Itb(ia,Jz(tv1,tv2),Sp(pia)), btb, im) where pia = btb[ia] Fetch-Load Rule Proc(ia, rf , rob, btb, im) if im[ia] = r:=Load(r1) ! Proc(ia+1, rf , rob Itb(ia,t :=Load(tv1,U),Wr(r)), btb, im) Fetch-Store Rule Proc(ia, rf , rob, btb, im) if im[ia] = Store(r1,r2) ! Proc(ia+1, rf , rob Itb(ia,t :=Store(tv1,tv2,U)), btb, im) As an example of instruction fetch rules, consider the Fetch-Op rule, which fetches an Op instruction and after register renaming simply puts it at the end of the rob. In all the instruction fetch rules, t represents an unused tag, tv1 and tv2 represent the tag or value corresponding to the operand registers r1 and r2, respectively, that is, tv1 =lookup(r1, rf , rob), tv2 = lookup(r2, rf , rob). Figure 2.5 summarizes the instruction fetch rules. Any implementation includes a nite number of rob entries, and the instruction fetch must be stalled if rob is full. This availability checking can be easily modeled. A fast implementation of the lookup procedure in hardware is quite di cult. Often a renaming table that retains the association between a register name and its current tag is maintained separately. 2.4.2 Arithmetic Operation and Value Propagation Rules The arithmetic operation rule states that an arithmetic operation in the rob can be performed if both operands are available. It assigns the result to the corresponding tag. Note that the instruction can be in any position in the rob. The forward rule sends a tag's value to other instruction templates, while the commit rule writes the value produced by the oldest instruction in the rob to the destination register and retires the corresponding renaming tag. Notation rob2[v/t] means that one or more appearances of tag t in rob2 are replaced by value v. Figure 2.6 summarizes the rules for arithmetic operation and value propagation. 34
Current State: Proc(ia, rf , rob, btb, im) Rule Name rob Next rob Next rf Op rob1 Itb(ia1,t :=Op(v1,v2),Wr(r)) rob2 rob1 Itb(ia1,t := Op(v1,v2),Wr(r)) rob2 rf Value-Forward rob1 Itb(ia1,t :=v,Wr(r)) rob2 (t 2 rob2) rob1 Itb(ia1,t :=v,Wr(r)) rob2[v/t] rf Value-Commit Itb(ia1,t :=v,Wr(r)) rob (t =2 rob) rob rf [r :=v] Figure 2.6: PS Arithmetic Operation and Value Propagation Rules Op Rule Proc(ia, rf , rob1 Itb(ia1,t :=Op(v1,v2),Wr(r)) rob2, btb, im) ! Proc(ia, rf , rob1 Itb(ia1,t :=v,Wr(r)) rob2, btb, im) where v =Op(v1,v2) Value-Forward Rule Proc(ia, rf , rob1 Itb(ia1,t :=v,Wr(r)) rob2, btb, im) if t 2 rob2 ! Proc(ia, rf , rob1 Itb(ia1,t :=v,Wr(r)) rob2[v/t], btb, im) Value-Commit Rule Proc(ia, rf , Itb(ia1,t :=v,Wr(r)) rob, btb, im) if t =2 rob ! Proc(ia, rf [r :=v], rob, btb, im) The rob pattern in the commit rule dictates that the register le can only be modi ed by the oldest instruction after it has forwarded the value to all the bu ers in the rob that reference its tag. Restricting the register update to just the oldest instruction in the rob eliminates output (write-after-write) hazards, and protects the register le from being polluted by incorrect speculative instructions. It also provides a way to support precise interrupts. The commit rule is needed to free up resources and to let the following instructions reuse the tag. 2.4.3 Branch Completion Rules The branch completion rules determine if the branch prediction was correct by comparing the predicted instruction address (pia) with the resolved branch targetinstruction address (nia or ia1+1). If they do not match (meaning the speculation was wrong), all instructions issued after the branch instruction are aborted, and the program counter is set to the new branch target instruction. The branch target bu er btb is updated according to some prediction algorithm btb 0 represents the new branch target bu er. Figure 2.7 summarizes the branch resolution cases. It is worth noting that the branch rules allow branches to be resolved in any order. Jump-CorrectSpec Rule Proc(ia, rf , rob1 Itb(ia1,Jz(0,nia),Sp(pia)) rob2, btb, im) if pia = nia ! Proc(ia, rf , rob1 rob2, btb 0 , im) Jump-WrongSpec Rule Proc(ia, rf , rob1 Itb(ia1,Jz(0,nia),Sp(pia)) rob2, btb, im) if pia 6= nia ! Proc(nia, rf , rob1, btb 0 , im) NoJump-CorrectSpec Rule Proc(ia, rf , rob1 Itb(ia1,Jz(v,-),Sp(pia)) rob2, btb, im) if v 6=0 ^ pia = ia1+1 ! Proc(ia, rf , rob1 rob2, btb 0 , im) 35
Page 1: CSAIL Computer Science and Artifici
Page 5: Design and Veri cation of Adaptive
Page 8 and 9: I am truly grateful to my parents f
Page 10 and 11: 4 The Base Cache Coherence Protocol
Page 13 and 14: List of Figures 1.1 Impact of Archi
Page 15 and 16: Chapter 1 Introduction Shared memor
Page 17 and 18: transparent and exposed only for lo
Page 19 and 20: Example 1: Can both registers r1 an
Page 21 and 22: and release locks, which guard ever
Page 23 and 24: that are interconnected with an o -
Page 25 and 26: although various techniques have be
Page 27 and 28: y showing that each processor can a
Page 29 and 30: s1 if p (s1) ! s2 where s1 and s2 a
Page 31 and 32: Program counter (pc) +1 Instruction
Page 33 and 34: Branch target buffer (btb) Program
Page 35: instruction is waiting to be dispat
Page 39 and 40: Rule Name mem pmb mpb Next mem Next
Page 41 and 42: Specification Implementation t 1 B
Page 43 and 44: Intuitively, \2P " means that \P is
Page 45 and 46: (a) (b) PC 1005 PC 2000 Instruction
Page 47 and 48: ewritten to s2 according to rule R.
Page 49 and 50: It can be shown that the relaxed di
Page 51 and 52: Chapter 3 The Commit-Reconcile & Fe
Page 53 and 54: Producer Storel(a,v) Commit(a) Cons
Page 55 and 56: Commit/Reconcile Purge Loadl/Commit
Page 57 and 58: instructions, because of the lack o
Page 59 and 60: CRF-Relaxed-Commit Rule Site(sache,
Page 61 and 62: 3.4 Universality of the CRF Model M
Page 63 and 64: Translation from CRF to PSO: The Fe
Page 65 and 66: proc proc proc pmb mpb pmb mpb pmb
Page 67 and 68: Chapter 4 The Base Cache Coherence
Page 69 and 70: can be classi ed into two non-overl
Page 71 and 72: arbitrarily in an outgoing queue (t
Page 73 and 74: 4.3 The Imperative Rules of the Bas
Page 75 and 76: Imperative Processor Rules Instruct
Page 77 and 78: Figure 4.5 de nes the rules of the
Page 79 and 80: 4.5.2 Mapping from Base to CRF We d
Page 81 and 82: Base Imperative Rule CRF Rule IP1 (
Page 83 and 84: Base Rule Base Imperative Rule P1 I
Page 85 and 86: eceives a CacheReq message, it will
Page 87 and 88:
e completed if it has an in nite nu
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SYS Sys(MSITE, SITEs) System MSITE
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Commit/Reconcile C-Receive-WbAck Ru
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message can be resumed eventually.
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If the memory state shows that the
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5.3.3 FIFO Message Passing The live
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Figure 5.7 gives the M-engine rules
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Backward-Message-Cache-to-Mem-for-W
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5.4.3 Simulation of WP in CRF Theor
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WP Imperative Rule CRF Rules IP1 (L
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WP Rule WP Imperative & Directive R
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(4) Msg(H,id ,Cache,a,-)" 2 Cin id(
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This completes the proof according
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emains as CachePending, there mustb
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M-engine Rules Msg from id Mstate A
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Chapter 6 The Migratory Cache Coher
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Commit/Reconcile Send Purge Loadl/C
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Mandatory Processor Rules Instructi
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while the memory sends a FlushReq m
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Lemma 38 D is strongly terminating
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Migratory Imperative Rule CRF Rules
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Cell(a,v,C[id ]) 2 Mem(s) _ Cell(a,
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According to Theorem-C and Lemma 45
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CacheReq message. In the latter cas
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Chapter 7 Cachet: A Seamless Integr
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7.1.1 Putting Things Together It is
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Writeback Operations In Cachet, a w
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Composite Message Equivalent Sequen
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Imperative Processor Rules Instruct
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Invalid Commit/Reconcile Receive Ca
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Composite Imperative C-engine Rules
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7.4 The Cachet Cache Coherence Prot
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Voluntary C-engine Rules Cstate Act
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The memory processes an incoming Ca
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The inaccuracy of memory states can
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C-engine Rule of Cachet Deriving Im
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Composite Mandatory Processor Rules
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memory regions simultaneously. In a
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Chapter 8 Conclusions This thesis h
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and heuristic policies. Mandatory r
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technique can be used to allow a ca
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Voluntary C-engine Rules Cstate Act
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FIFO Message Passing msg1 msg2 msg2
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[13] J. K. Archibald. The Cache Coh
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[41] A. Erlichson, N. Nuckolls, G.
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[71] J. Kuskin, D. Ofelt, M. Heinri
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[101] F. Pong and M. Dubois. A New
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Design and Verification of Adaptive Cache Coherence Protocols ...

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