Design and Verification of Adaptive Cache Coherence Protocols ...

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Maintaining coarse-grain coherence states can reduce the implementation cost because less state information is recorded at the cache and memory side. It is worth pointing out that cache coherence protocols with coarse-grain states can be derived from protocols with ne-grain states such as Cachet. Both the soundness and liveness of the derived protocols are automatically guaranteed since all the coherence operations are legal mandatory or voluntary operations. 160
Chapter 8 Conclusions This thesis has addressed several important issues regarding cache coherence protocols for shared memory multiprocessor systems. First, what memory model should be supported to allow e cient and exible implementations second, what adaptivity can be provided to accom- modate programs with di erent access patterns and third, how adaptivecache coherence protocols can be designed and veri ed. We have proposed a scalable mechanism-oriented memory model called Commit-Reconcile & Fences (CRF), and developed an adaptive cache coherence protocol called Cachet that implements CRF in DSM system. Our research uses Term Rewrit- ing Systems (TRSs) as the formalism to precisely specify memory models and cache coherence protocols. The CRF memory model exposes data replication via a notion of semantic caches, referred to as saches. There are three types of memory instructions: memory access instructions Loadl and Storel, memory rendezvous instructions Commit and Reconcile, and memory fence instructions. Semantically, each processor is associated with a sache that contains a set of cells. Each sache cell has a state, which can be either Clean or Dirty. The Clean state indicates that the data has not been modi ed since it was cached or last written back, while the Dirty state indicates that the data has been modi ed and has not been written back to the memory since then. At any time, a sache can purge a Clean copy from the sache, write a Dirty copyback to the memory, or retrieve a Clean copy from the memory for an uncached address. A Commit instruction cannot be completed if the address is cached in the Dirty state, and a Reconcile instruction cannot be completed if the address is cached in the Clean state. There are good reasons to be skeptical of yet another memory model. Memory model de nitions in modern microprocessor manuals are sometimes imprecise, ambiguous or even wrong. Not only computer architects, but also compiler writers and system programmers, would prefer memory models to be simpler and cleaner at the architecture level. The CRF model can eliminate some modele de l'annee disadvantages of existing memory models. Programs written under sequential consistency and various weaker memory models can be translated into e cient CRF programs, while most existing parallel systems can be interpreted as speci c implementations of CRF, though more e cient implementations are possible. Indeed, the 161
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CSAIL Computer Science and Artifici
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Design and Veri cation of Adaptive
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I am truly grateful to my parents f
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4 The Base Cache Coherence Protocol
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List of Figures 1.1 Impact of Archi
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Chapter 1 Introduction Shared memor
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transparent and exposed only for lo
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Example 1: Can both registers r1 an
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and release locks, which guard ever
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that are interconnected with an o -
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although various techniques have be
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y showing that each processor can a
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s1 if p (s1) ! s2 where s1 and s2 a
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Program counter (pc) +1 Instruction
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Branch target buffer (btb) Program
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instruction is waiting to be dispat
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Current State: Proc(ia, rf , rob, b
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Rule Name mem pmb mpb Next mem Next
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Specification Implementation t 1 B
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Intuitively, \2P " means that \P is
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(a) (b) PC 1005 PC 2000 Instruction
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ewritten to s2 according to rule R.
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It can be shown that the relaxed di
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Chapter 3 The Commit-Reconcile & Fe
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Producer Storel(a,v) Commit(a) Cons
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Commit/Reconcile Purge Loadl/Commit
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instructions, because of the lack o
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CRF-Relaxed-Commit Rule Site(sache,
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3.4 Universality of the CRF Model M
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Translation from CRF to PSO: The Fe
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proc proc proc pmb mpb pmb mpb pmb
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Chapter 4 The Base Cache Coherence
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can be classi ed into two non-overl
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arbitrarily in an outgoing queue (t
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4.3 The Imperative Rules of the Bas
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Imperative Processor Rules Instruct
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Figure 4.5 de nes the rules of the
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4.5.2 Mapping from Base to CRF We d
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Base Imperative Rule CRF Rule IP1 (
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Base Rule Base Imperative Rule P1 I
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eceives a CacheReq message, it will
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e completed if it has an in nite nu
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SYS Sys(MSITE, SITEs) System MSITE
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Commit/Reconcile C-Receive-WbAck Ru
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message can be resumed eventually.
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If the memory state shows that the
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5.3.3 FIFO Message Passing The live
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Figure 5.7 gives the M-engine rules
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Backward-Message-Cache-to-Mem-for-W
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5.4.3 Simulation of WP in CRF Theor
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WP Imperative Rule CRF Rules IP1 (L
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WP Rule WP Imperative & Directive R
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(4) Msg(H,id ,Cache,a,-)" 2 Cin id(
Page 111 and 112: This completes the proof according
Page 113 and 114: emains as CachePending, there mustb
Page 115 and 116: M-engine Rules Msg from id Mstate A
Page 117 and 118: Chapter 6 The Migratory Cache Coher
Page 119 and 120: Commit/Reconcile Send Purge Loadl/C
Page 121 and 122: Mandatory Processor Rules Instructi
Page 123 and 124: while the memory sends a FlushReq m
Page 125 and 126: Lemma 38 D is strongly terminating
Page 127 and 128: Migratory Imperative Rule CRF Rules
Page 129 and 130: Cell(a,v,C[id ]) 2 Mem(s) _ Cell(a,
Page 131 and 132: According to Theorem-C and Lemma 45
Page 133 and 134: CacheReq message. In the latter cas
Page 135 and 136: Chapter 7 Cachet: A Seamless Integr
Page 137 and 138: 7.1.1 Putting Things Together It is
Page 139 and 140: Writeback Operations In Cachet, a w
Page 141 and 142: Composite Message Equivalent Sequen
Page 143 and 144: Imperative Processor Rules Instruct
Page 145 and 146: Invalid Commit/Reconcile Receive Ca
Page 147 and 148: Composite Imperative C-engine Rules
Page 149 and 150: 7.4 The Cachet Cache Coherence Prot
Page 151 and 152: Voluntary C-engine Rules Cstate Act
Page 153 and 154: The memory processes an incoming Ca
Page 155 and 156: The inaccuracy of memory states can
Page 157 and 158: C-engine Rule of Cachet Deriving Im
Page 159 and 160: Composite Mandatory Processor Rules
Page 161: memory regions simultaneously. In a
Page 165 and 166: and heuristic policies. Mandatory r
Page 167 and 168: technique can be used to allow a ca
Page 169 and 170: Voluntary C-engine Rules Cstate Act
Page 171 and 172: FIFO Message Passing msg1 msg2 msg2
Page 173 and 174: [13] J. K. Archibald. The Cache Coh
Page 175 and 176: [41] A. Erlichson, N. Nuckolls, G.
Page 177 and 178: [71] J. Kuskin, D. Ofelt, M. Heinri
Page 179 and 180: [101] F. Pong and M. Dubois. A New
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Design and Verification of Adaptive Cache Coherence Protocols ...

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