Design and Verification of Adaptive Cache Coherence Protocols ...

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Current State: Proc(ia, rf , rob, btb, im) Rule Name rob = rob1 Itb(ia1,Jz(0,nia),Sp(pia)) rob2 Next rob Next pc Jump-CorrectSpec pia = nia rob1 rob2 ia Jump-WrongSpec pia 6= nia rob1 nia Rule Name rob = rob1 Itb(ia1,Jz(v,-),Sp(pia)) rob2 Next rob Next pc NoJump-CorrectSpec v 6=0, pia = ia1+1 rob1 rob2 ia NoJump-WrongSpec v 6=0, pia 6= ia1+1 rob1 ia1+1 Figure 2.7: PS Branch Completion Rules Current State: Sys(Proc(ia, rf , rob1 itb rob2, btb, im), pmb, mpb, mem) Rule Name itb pmb Next itb Next pmb Dispatch-Load Itb(ia1,t :=Load(a,U),Wr(r)) pmb Itb(ia1,t :=Load(a,D),Wr(r)) pmbht,Load(a)i U, Jz =2 rob1 Dispatch-Store Itb(ia1,t :=Store(a,v,U)) pmb Itb(ia1,t :=Store(a,v,D)) pmbht,Store(a,v)i U, Jz =2 rob1 Rule Name itb mpb Next itb Next mpb Retire-Load Itb(ia1,t :=Load(a,D),Wr(r)) ht,vijmpb Itb(ia1,t :=v,Wr(r)) mpb Retire-Store Itb(ia1,t :=Store(a,v,D)) ht,Ackijmpb (deleted) mpb Figure 2.8: PS Memory Instruction Dispatch and Completion Rules NoJump-WrongSpec Rule Proc(ia, rf , rob1 Itb(ia1,Jz(v,-),Sp(pia)) rob2, btb, im) if v 6=0 ^ pia 6= ia1+1 ! Proc(ia1+1, rf , rob1, btb 0 , im) The branch resolution mechanism becomes slightly complicated if certain instructions that need to be killed are waiting for responses from the memory system or some functional units. In such a situation, killing may have to be postponed until rob2 does not contain an instruction waiting for a response. (This is not possible for the rules that we have presented). 2.4.4 Memory Access Rules Memory requests are sent to the memory system strictly in order. A request is sent only when there is no unresolved branch instruction in front of it. The dispatch rules ip the U bit to D and enqueue the memory request into the pmb. The memory system can respond to the requests in any order and the response is used to update the appropriate entry in the rob. The semicolon is used to represent an ordered queue and the vertical bar an unordered queue (that is, the connective is both commutative and associative). Figure 2.8 summarizes the memory instruction dispatch and completion rules. Dispatch-Load Rule Sys(Proc(ia, rf , rob1 Itb(ia1,t :=Load(a,U),Wr(r)) rob2, btb, im), pmb, mpb, mem) if Jz, U =2 rob1 ! Sys(Proc(ia, rf , rob1 Itb(ia1,t :=Load(a,D),Wr(r)) rob2, btb, im), pmbht,Load(a)i, mpb, 36 mem)
Rule Name mem pmb mpb Next mem Next pmb Next mpb Load-Memory mem ht,Load(a)ipmb mpb mem pmb mpbjht,mem[a]i Store-Memory mem ht,Store(a,v)ipmb mpb mem[a:=v] pmb mpbjht,Acki Figure 2.9: A Simple Processor-Memory Interface Dispatch-Store Rule Sys(Proc(ia, rf , rob1 Itb(ia1,t :=Store(a,v,U)) rob2, btb, im), pmb, mpb, mem) if Jz, U =2 rob1 ! Sys(Proc(ia, rf , rob1 Itb(ia1,t :=Store(a,v,D)) rob2, btb, im), pmbht,Store(a,v)i, mpb, mem) Retire-Load Rule Sys(Proc(ia, rf , rob1 Itb(ia1,t :=Load(a,D),Wr(r)) rob2, btb, im), pmb, ht,vijmpb, mem) ! Sys(Proc(ia, rf , rob1 Itb(ia1,t :=v,Wr(r)) rob2, btb, im), pmb, mpb, mem) Retire-Store Rule Sys(Proc(ia, rf , rob1 Itb(ia1,t :=Store(a,v,D)) rob2, btb, im), pmb, ht,Ackijmpb, mem) ! Sys(Proc(ia, rf , rob1 rob2, btb, im), pmb, mpb, mem) We de ne a simple interface between the processor and the memory that ensures memory accesses are processed in order to guarantee sequential consistency in multiprocessor systems. Figure 2.9 summarizes the rules for how the memory system handles memory requests from the pmb. More aggressive implementations of memory access operations are possible, but they often lead to various relaxed memory models in multiprocessor systems. Load-Memory Rule Sys(proc, ht,Load(a)ipmb, mpb, mem) ! Sys(proc, pmb, mpbjht,mem[a]i, mem) Store-Memory Rule Sys(proc, ht,Store(a,v)ipmb, mpb, mem) ! Sys(proc, pmb, mpbjht,Acki, mem[a:=v]) 2.5 Using TRS to Prove Correctness TRSs o er a convenient way to describe asynchronous systems and can be used to prove the correctness of an implementation with respect to a speci cation. The correctness of an implementation can be described in terms of soundness and liveness properties. A soundness property ensures that the implementation cannot take an action that is inconsistent with the speci cation, that is, something bad does not happen. A liveness property ensures that the implementation makes progress eventually, that is, something good does eventually happen. 37
Page 1: CSAIL Computer Science and Artifici
Page 5: Design and Veri cation of Adaptive
Page 8 and 9: I am truly grateful to my parents f
Page 10 and 11: 4 The Base Cache Coherence Protocol
Page 13 and 14: List of Figures 1.1 Impact of Archi
Page 15 and 16: Chapter 1 Introduction Shared memor
Page 17 and 18: transparent and exposed only for lo
Page 19 and 20: Example 1: Can both registers r1 an
Page 21 and 22: and release locks, which guard ever
Page 23 and 24: that are interconnected with an o -
Page 25 and 26: although various techniques have be
Page 27 and 28: y showing that each processor can a
Page 29 and 30: s1 if p (s1) ! s2 where s1 and s2 a
Page 31 and 32: Program counter (pc) +1 Instruction
Page 33 and 34: Branch target buffer (btb) Program
Page 35 and 36: instruction is waiting to be dispat
Page 37: Current State: Proc(ia, rf , rob, b
Page 41 and 42: Specification Implementation t 1 B
Page 43 and 44: Intuitively, \2P " means that \P is
Page 45 and 46: (a) (b) PC 1005 PC 2000 Instruction
Page 47 and 48: ewritten to s2 according to rule R.
Page 49 and 50: It can be shown that the relaxed di
Page 51 and 52: Chapter 3 The Commit-Reconcile & Fe
Page 53 and 54: Producer Storel(a,v) Commit(a) Cons
Page 55 and 56: Commit/Reconcile Purge Loadl/Commit
Page 57 and 58: instructions, because of the lack o
Page 59 and 60: CRF-Relaxed-Commit Rule Site(sache,
Page 61 and 62: 3.4 Universality of the CRF Model M
Page 63 and 64: Translation from CRF to PSO: The Fe
Page 65 and 66: proc proc proc pmb mpb pmb mpb pmb
Page 67 and 68: Chapter 4 The Base Cache Coherence
Page 69 and 70: can be classi ed into two non-overl
Page 71 and 72: arbitrarily in an outgoing queue (t
Page 73 and 74: 4.3 The Imperative Rules of the Bas
Page 75 and 76: Imperative Processor Rules Instruct
Page 77 and 78: Figure 4.5 de nes the rules of the
Page 79 and 80: 4.5.2 Mapping from Base to CRF We d
Page 81 and 82: Base Imperative Rule CRF Rule IP1 (
Page 83 and 84: Base Rule Base Imperative Rule P1 I
Page 85 and 86: eceives a CacheReq message, it will
Page 87 and 88: e completed if it has an in nite nu
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SYS Sys(MSITE, SITEs) System MSITE
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Commit/Reconcile C-Receive-WbAck Ru
Page 93 and 94:
message can be resumed eventually.
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If the memory state shows that the
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5.3.3 FIFO Message Passing The live
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Figure 5.7 gives the M-engine rules
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Backward-Message-Cache-to-Mem-for-W
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5.4.3 Simulation of WP in CRF Theor
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WP Imperative Rule CRF Rules IP1 (L
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WP Rule WP Imperative & Directive R
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(4) Msg(H,id ,Cache,a,-)" 2 Cin id(
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This completes the proof according
Page 113 and 114:
emains as CachePending, there mustb
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M-engine Rules Msg from id Mstate A
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Chapter 6 The Migratory Cache Coher
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Commit/Reconcile Send Purge Loadl/C
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Mandatory Processor Rules Instructi
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while the memory sends a FlushReq m
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Lemma 38 D is strongly terminating
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Migratory Imperative Rule CRF Rules
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Cell(a,v,C[id ]) 2 Mem(s) _ Cell(a,
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According to Theorem-C and Lemma 45
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CacheReq message. In the latter cas
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Chapter 7 Cachet: A Seamless Integr
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7.1.1 Putting Things Together It is
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Writeback Operations In Cachet, a w
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Composite Message Equivalent Sequen
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Imperative Processor Rules Instruct
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Invalid Commit/Reconcile Receive Ca
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Composite Imperative C-engine Rules
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7.4 The Cachet Cache Coherence Prot
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Voluntary C-engine Rules Cstate Act
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The memory processes an incoming Ca
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The inaccuracy of memory states can
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C-engine Rule of Cachet Deriving Im
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Composite Mandatory Processor Rules
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memory regions simultaneously. In a
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Chapter 8 Conclusions This thesis h
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and heuristic policies. Mandatory r
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technique can be used to allow a ca
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Voluntary C-engine Rules Cstate Act
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FIFO Message Passing msg1 msg2 msg2
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[13] J. K. Archibald. The Cache Coh
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[41] A. Erlichson, N. Nuckolls, G.
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[71] J. Kuskin, D. Ofelt, M. Heinri
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[101] F. Pong and M. Dubois. A New
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