Design and Verification of Adaptive Cache Coherence Protocols ...

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5.5.1 Some Invariants of WP Lemma26isidentical to Lemma 15, except that the T[dir, ] state used in the imperative rules is replaced by the C[dir] andT[dir, ] states used in the integrated rules. Lemma 26 Given a WP term s, (1) Cell(a,v,C[id j-]) 2 Mem(s) _ Cell(a,v,T[id j-,-]) 2 Mem(s) , Cell(a,v,Clean) 2 Cache id(s) _ Cell(a,-,Dirty) 2 Cache id(s) _ Msg(H,id ,Cache,a,v) 2 MoutCin id (s) _ Msg(H,id ,WbAck,a) 2 MoutCin id (s) _ Msg(id ,H,Purge,a) 2 MinCout id (s) _ Msg(id ,H,Wb,a,-) 2 MinCout id (s) (2) Cell(a,v,WbPending) 2 Cache id(s) , Msg(id ,H,Wb,a,v) 2 MinCout id (s) _ Cell(a,-,T[-,(id ,v)j-]) 2 Mem(s) _ Msg(H,id ,WbAck,a) 2 MoutCin id (s) _ Msg(H,id ,FlushAck,a) 2 MoutCin id (s) Lemma 27 includes invariants regarding message generation and processing. Invariants (1)-(2) ensure that when a Loadl or Storel instruction is performed on an uncached address, the cache will contain a clean cell for the address, or issue a CacheReq message and set the cache state to CachePending. Invariant (3) ensures that when a Commit instruction is performed on a dirty cell, the cache will issue a Wb message and set the cache state to WbPending. The proof follows from the weak fairness of Rules P5, P10 and P12. Invariants (4)-(8) ensure that when a cache receives a Cache or WbAck message, it will set the cache state to Clean when a cache receives a FlushAck message, it will purge the address when a cache receives a PurgeReq message, it will send a Purge or Wb message depending on whether a clean or dirty copy is cached for the address. The proof follows from the weak fairness of Rules MC1, MC2, MC3, MC4, MC5 and MC6. Invariants (9)-(11) ensure that when the memory receives a Purge message, it will remove the cache identi er from the directory when the memory receives a Wb message, it will sus- pend the message when the directory becomes empty, the memory will resume a suspended message. The proof follows from the weak fairness of Rules MM5, MM6, MM7, MM8 and MM9. Notation dir;id represents a directory that does not contains identi er id . Invariants (12)-(13) ensure that each outgoing message will be delivered to its destination's incoming queue. This can be proved by simple induction on the number of preceding messages in the outgoing queue (note that the message passing rules are weakly fair). Lemma 27 Given a WP sequence , (1) ht,Loadl(a)i2Pmb id( ) ^ a =2 Cache id( ) Cell(a,-,Clean) 2 Cache id( ) _ (Cell(a,-,CachePending) 2 Cache id( ) ^ Msg(id ,H,CacheReq,a) 2 Cout id ( )) (2) ht,Storel(a,-)i2Pmb id( ) ^ a =2 Cache id( ) Cell(a,-,Clean) 2 Cache id( ) _ (Cell(a,-,CachePending) 2 Cache id( ) ^ Msg(id ,H,CacheReq,a) 2 Cout id ( )) (3) ht,Commit(a)i2Pmb id ( ) ^ Cell(a,-,Dirty) 2 Cache id( ) Cell(a,-,WbPending) 2 Cache id( ) ^ Msg(id ,H,Wb,a,-) 2 Cout id ( ) 106
(4) Msg(H,id ,Cache,a,-)" 2 Cin id( ) Cell(a,-,Clean) 2 Cache id( ) (5) Msg(H,id ,WbAck,a)" 2 Cin id ( ) Cell(a,-,Clean) 2 Cache id( ) (6) Msg(H,id ,FlushAck,a)" 2 Cin id( ) a =2 Cache id( ) (7) Msg(H,id ,PurgeReq,a)" 2 Cin id( ) ^ Cell(a,-,Clean) 2 Cache id( ) Msg(id ,H,Purge,a) 2 Cout id( ) (8) Msg(H,id ,PurgeReq,a)" 2 Cin id( ) ^ Cell(a,-,Dirty) 2 Cache id( ) Msg(id ,H,Wb,a,-) 2 Cout id ( ) (9) Msg(id ,H,Purge,a)" 2 Min( ) Cell(a,-,C[dir;id]) 2 Mem( ) _ Cell(a,-,T[dir;id,-]) 2 Mem( ) (10) Msg(id ,H,Wb,a,-)" 2 Min( ) Cell(a,-,T[dir;id,(id ,-)j-]) 2 Mem( ) (11) Cell(a,-,T[ ,(id ,-)j-]) 2 Mem( ) Msg(H,id ,WbAck,a) 2 Mout( ) _ Msg(H,id ,FlushAck,a) 2 Mout( ) (12) msg 2 Cout id( ) ^ Dest(msg)=H msg 2 Min( ) (13) msg 2 Mout( ) ^ Dest(msg)=id msg 2 Cin id ( ) Lemma 28 ensures that an incoming Cache, WbAck, FlushAck, PurgeReq, Purge or Wb message will eventually become the rst message regarding the address in the incoming queue. This implies that the message will be brought to the front end of the incoming queue so that it has an opportunity to be processed. A more general proposition will be presented in Lemma 31, which guarantees that any incoming message will eventually become the rst message in the incoming queue. Lemma 28 Given a WP sequence , (1) msg 2 Cin id( ) msg" 2 Cin id( ) (2) msg 2 Min( ) ^ (Cmd(msg) = Purge _ Cmd(msg)=Wb) msg" 2 Min( ) Proof The proof is based on induction on the number of messages that are in front the message in the incoming queue. It is obvious that the rst message in a cache's incoming queue can always be processed because of the weak fairness of the mandatory cache engine rules. At the memory side, the rst incoming message can always be processed except that a CacheReq message may need to be stalled. The key observation here is that a CacheReq message followed by a Purge or Wb message cannot be stalled. This is because according to Lemma 26, the directory of the memory state contains the cache identi er, which implies that the CacheReq message can be processed according to Rule MM2 or MM4. 2 Lemma 29 ensures that if a memory cell is in a transient state and the directory shows that the address is cached in a cache, then the cache's identi er will be removed from the directory eventually. This guarantees that suspended writeback messages will be resumed. Lemma 29 Given a WP sequence , Cell(a,-,T[id j-,-]) 2 Mem( ) Cell(a,-,T[dir;id,-]) 2 Mem( ) 107
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CSAIL Computer Science and Artifici
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Design and Veri cation of Adaptive
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I am truly grateful to my parents f
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4 The Base Cache Coherence Protocol
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List of Figures 1.1 Impact of Archi
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Chapter 1 Introduction Shared memor
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transparent and exposed only for lo
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Example 1: Can both registers r1 an
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and release locks, which guard ever
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that are interconnected with an o -
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although various techniques have be
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y showing that each processor can a
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s1 if p (s1) ! s2 where s1 and s2 a
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Program counter (pc) +1 Instruction
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Branch target buffer (btb) Program
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instruction is waiting to be dispat
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Current State: Proc(ia, rf , rob, b
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Rule Name mem pmb mpb Next mem Next
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Specification Implementation t 1 B
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Intuitively, \2P " means that \P is
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(a) (b) PC 1005 PC 2000 Instruction
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ewritten to s2 according to rule R.
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It can be shown that the relaxed di
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Chapter 3 The Commit-Reconcile & Fe
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Producer Storel(a,v) Commit(a) Cons
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Commit/Reconcile Purge Loadl/Commit
Page 57 and 58: instructions, because of the lack o
Page 59 and 60: CRF-Relaxed-Commit Rule Site(sache,
Page 61 and 62: 3.4 Universality of the CRF Model M
Page 63 and 64: Translation from CRF to PSO: The Fe
Page 65 and 66: proc proc proc pmb mpb pmb mpb pmb
Page 67 and 68: Chapter 4 The Base Cache Coherence
Page 69 and 70: can be classi ed into two non-overl
Page 71 and 72: arbitrarily in an outgoing queue (t
Page 73 and 74: 4.3 The Imperative Rules of the Bas
Page 75 and 76: Imperative Processor Rules Instruct
Page 77 and 78: Figure 4.5 de nes the rules of the
Page 79 and 80: 4.5.2 Mapping from Base to CRF We d
Page 81 and 82: Base Imperative Rule CRF Rule IP1 (
Page 83 and 84: Base Rule Base Imperative Rule P1 I
Page 85 and 86: eceives a CacheReq message, it will
Page 87 and 88: e completed if it has an in nite nu
Page 89 and 90: SYS Sys(MSITE, SITEs) System MSITE
Page 91 and 92: Commit/Reconcile C-Receive-WbAck Ru
Page 93 and 94: message can be resumed eventually.
Page 95 and 96: If the memory state shows that the
Page 97 and 98: 5.3.3 FIFO Message Passing The live
Page 99 and 100: Figure 5.7 gives the M-engine rules
Page 101 and 102: Backward-Message-Cache-to-Mem-for-W
Page 103 and 104: 5.4.3 Simulation of WP in CRF Theor
Page 105 and 106: WP Imperative Rule CRF Rules IP1 (L
Page 107: WP Rule WP Imperative & Directive R
Page 111 and 112: This completes the proof according
Page 113 and 114: emains as CachePending, there mustb
Page 115 and 116: M-engine Rules Msg from id Mstate A
Page 117 and 118: Chapter 6 The Migratory Cache Coher
Page 119 and 120: Commit/Reconcile Send Purge Loadl/C
Page 121 and 122: Mandatory Processor Rules Instructi
Page 123 and 124: while the memory sends a FlushReq m
Page 125 and 126: Lemma 38 D is strongly terminating
Page 127 and 128: Migratory Imperative Rule CRF Rules
Page 129 and 130: Cell(a,v,C[id ]) 2 Mem(s) _ Cell(a,
Page 131 and 132: According to Theorem-C and Lemma 45
Page 133 and 134: CacheReq message. In the latter cas
Page 135 and 136: Chapter 7 Cachet: A Seamless Integr
Page 137 and 138: 7.1.1 Putting Things Together It is
Page 139 and 140: Writeback Operations In Cachet, a w
Page 141 and 142: Composite Message Equivalent Sequen
Page 143 and 144: Imperative Processor Rules Instruct
Page 145 and 146: Invalid Commit/Reconcile Receive Ca
Page 147 and 148: Composite Imperative C-engine Rules
Page 149 and 150: 7.4 The Cachet Cache Coherence Prot
Page 151 and 152: Voluntary C-engine Rules Cstate Act
Page 153 and 154: The memory processes an incoming Ca
Page 155 and 156: The inaccuracy of memory states can
Page 157 and 158: C-engine Rule of Cachet Deriving Im
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Composite Mandatory Processor Rules
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memory regions simultaneously. In a
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Chapter 8 Conclusions This thesis h
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and heuristic policies. Mandatory r
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technique can be used to allow a ca
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Voluntary C-engine Rules Cstate Act
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FIFO Message Passing msg1 msg2 msg2
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[13] J. K. Archibald. The Cache Coh
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[41] A. Erlichson, N. Nuckolls, G.
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[71] J. Kuskin, D. Ofelt, M. Heinri
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[101] F. Pong and M. Dubois. A New
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Design and Verification of Adaptive Cache Coherence Protocols ...

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