Design and Verification of Adaptive Cache Coherence Protocols ...

Commit/Reconcile
Invalid
Send Purge
Send CacheReq Cache- Receive Cache
Pending
Loadl/Commit/Reconcile Storel
Loadl/Storel/Reconcile
Wb-
Clean Receive WbAck Pending Send Wb Dirty
Receive Cache Receive FlushAck
Figure 5.6: Cache State Transitions of WP
On the other hand, a cache responds to a purge request on a clean cell by purging the clean
data and sending a Purge message to the memory. In the case that the cache copy is dirty, the
dirty copy is forced to be written back via a Wb message.
5.3.2 Voluntary Rules
At any time, a cache can purge a clean cell, and notify the memory of the purge operation
via a Purge message. It can also write a dirty copy back to the memory via a Wb message.
Furthermore, a cache can send a message to the memory to request a data copy forany uncached
address, even though no Loadl or Storel instruction is performed. Figure 5.6 shows the cache
state transitions of WP.
The memory can voluntarily send a data copy to any cache, provided the directory shows
that the address is not cached in that cache. This implies that a cache may receive a data copy
even though it has not requested for it. The memory can also voluntarily multicast a purge
request to purge clean copies of an address.
The voluntary rules allow the memory to supply a data copy without a request from the cache,
and a cache to purge or write back a data copy without a request from the memory. This
can cause unexpected situations if a request is received after the requested action has been
performed. For example,
Simultaneous Cache and CacheReq. Suppose initially the address is not cached in a cache
site. The memory sends a Cache message to the cache, while the cache sends a CacheReq
message to the memory. The CacheReq message will be discarded when it is received at
the memory (Rules MM2 & MM4).
Simultaneous Purge and PurgeReq. Suppose initially a clean copy of the address is cached
in a cache site. The cache purges the clean copy and sends a Purge message to the memory,
while the memory sends a PurgeReq message to the cache. The PurgeReq message will
be discarded when it is received at the cache (Rules MC8 & MC9).
Simultaneous Wb and PurgeReq. Suppose initially a dirty copy of the address is cached in
acache site. The cache sends a Wb message to write the dirty copyback to the memory,
while the memory sends a PurgeReq message to the cache. The PurgeReq message will
be discarded when it is received at the cache (Rule MC7).
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