Design and Verification of Adaptive Cache Coherence Protocols ...

and release locks, which guard every shared writable variable. One of the powers of sequential
consistency is that the lock operations can be de ned in the model itself. When used properly,
locks ensure that only one processor at a time can access a shared variable (though it is often
safe to read a shared variable without acquiring the lock).
It is common practice in parallel programming to use semaphores to synchronize concurrent
processes or threads properly to avoid data races. A data race occurs when there are multiple
concurrent accesses to a shared variable, at least one of which is a write operation. Intuitively,
a program is properly-synchronized if it contains enough synchronization operations so that
con icting memory accesses are always ordered by synchronization operations (that is, data
races are limited to acquiring semaphores).
It is possible to relax some constraints of sequential consistency in many sections of prop-
erly synchronized programs. Program-oriented memory models allow memory accesses to be
reordered and store operations to be performed in some non-atomic fashion based on the com-
mon intuition that properly-synchronized programs can behave sequentially consistent on an
architecture supporting some relaxed memory model. Although it is generally undecidable if
a program is properly-synchronized, it is often relatively convenient for the programmer to
characterize each memory operation as ordinary or synchronization access.
Program-oriented memory models can be often de ned in terms of some synchronization
constraints on the program. The system guarantees to appear sequentially consistent provided
that the program conforms to the synchronization constraints [2, 3, 47]. The intuition behind
is that we can ensure sequential consistency for properly-synchronized programs by just placing
coherence restrictions on synchronizations. Therefore, the programmer can rely on sequential
consistency to reason about the program, although the memory access operations are performed
in some out-of-order and non-atomic fashion.
Program-oriented memory models usually require that ordinary memory access operations
be distinguished from synchronization operations. Furthermore, di erent synchronization op-
erations can be exposed in di erent forms, which canhave di erent coherence implications on
implementations. Synchronization operations can be classi ed as acquire and release opera-
tions, loop and non-loop operations, and so on. Based on such classi cation, notions such as
Data-Race-Free programs [2, 3] and Properly-Labeled programs [47, 46] have beendeveloped.
Data-Race-Free-0 [2] only draws distinction between ordinary accesses and synchronizations.
A program obeys Data-Race-Free-0 if, for any sequentially consistent execution, all con icting
memory accesses are ordered by the transitive relation of program order and synchronization
order. Data-Race-Free-1 [3] furthermore characterizes paired synchronizations as acquire and
release operations. The Properly-Labeled programs [46, 47] can classify competing accesses
as loop and non-loop accesses, requiring the identi cation of a common class of synchroniza-
tion accesses where one processor repeatedly reads a location until another processor writes a
particular value to that location.
Dag consistency [17, 18] is a memory model that is de ned on the directed acyclic graph
(dag) of user-level threads that make up a parallel computation. Intuitively, each thread ob-
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