Design and Verification of Adaptive Cache Coherence Protocols ...

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superscalar execution and many others. All these features add complexity to the architec- ture and interact with each other, making the veri cation task more di cult. In recent years, considerable attention has focused on formal speci cation and veri cation of architec- tures [22, 23, 32, 57, 88, 104, 123]. For example, Burch and Dill [23] described a technique which automatically compares a pipelined implementation to an architectural speci cation and pro- duces debugging information for incorrect processor design. Levitt and Olukotun [80] proposed a methodology that iteratively de-constructs a pipeline by merging adjacent pipeline stages thereby allowing veri cations to be done in a number of easier steps. Windley [123] presented a case study which uses abstract theories to hierarchically verify microprocessor implementations formalized in HOL. Windley's methodology is similar to ours in the sense that the correctness theorem states the implementation implies the behavior speci cation. The most critical step in the proof is the de nition of the abstract mapping function to map the states of the implementation system into the states of the speci cation system. Our mapping functions based on draining rules are more intuitive because of the use of TRSs. 48
Chapter 3 The Commit-Reconcile & Fences Memory Model CRF (Commit-Reconcile & Fences) is a mechanism-oriented memory model and intended for architects and compiler writers rather than for high-level parallel programming. It is de ned by giving algebraic semantics to the memory related instructions so that every CRF program has a well-de ned operational behavior. The CRF mechanisms give architects great exibility for e cient implementations, and give compiler writers all the control they need. They can be incorporated in stages in future systems without loss of compatibility with existing systems. In Section 3.1 we de ne the CRF memory model using Term Rewriting Systems. We then present some derived rules of CRF in Section 3.2, and discuss coarse-grain CRF instructions in Section 3.3. Section 3.4 demonstrates the universality ofCRFby showing that programs under many existing memory models can be translated into CRF programs, and CRF programs can run e ciently on many existing systems. A generalized model of CRF is presented in Section 3.5, which allows writeback operations to be performed in di erent orders with respect to di erent cache sites. 3.1 The CRF Model The CRF model has a semantic notion of caches, referred to as saches, which makes the operational behavior of data replication to be part of the model. Figure 3.1 gives the CRF instructions. The CRF instructions can be classi ed into three categories: memory access instructions Loadl (load-local) and Storel (store-local), memory rendezvous instructions Com- mit and Reconcile, and memory fence instructions. There are four types of memory fences: Fencerr, Fencerw, Fencewr and Fenceww, which correspond to read-read, read-write, write-read, and write-write fences, respectively. CRF exposes both data replication and instruction reordering at the Instruction Set Archi- tecture (ISA) level. Figure 3.2 gives the system con guration of CRF. The system contains a memory and a set of sites. Each site has a semantic cache, on which Loadl and Storel instructions operate. The Commit and Reconcile instructions can be used to ensure that the data 49
Page 1: CSAIL Computer Science and Artifici
Page 5: Design and Veri cation of Adaptive
Page 8 and 9: I am truly grateful to my parents f
Page 10 and 11: 4 The Base Cache Coherence Protocol
Page 13 and 14: List of Figures 1.1 Impact of Archi
Page 15 and 16: Chapter 1 Introduction Shared memor
Page 17 and 18: transparent and exposed only for lo
Page 19 and 20: Example 1: Can both registers r1 an
Page 21 and 22: and release locks, which guard ever
Page 23 and 24: that are interconnected with an o -
Page 25 and 26: although various techniques have be
Page 27 and 28: y showing that each processor can a
Page 29 and 30: s1 if p (s1) ! s2 where s1 and s2 a
Page 31 and 32: Program counter (pc) +1 Instruction
Page 33 and 34: Branch target buffer (btb) Program
Page 35 and 36: instruction is waiting to be dispat
Page 37 and 38: Current State: Proc(ia, rf , rob, b
Page 39 and 40: Rule Name mem pmb mpb Next mem Next
Page 41 and 42: Specification Implementation t 1 B
Page 43 and 44: Intuitively, \2P " means that \P is
Page 45 and 46: (a) (b) PC 1005 PC 2000 Instruction
Page 47 and 48: ewritten to s2 according to rule R.
Page 49: It can be shown that the relaxed di
Page 53 and 54: Producer Storel(a,v) Commit(a) Cons
Page 55 and 56: Commit/Reconcile Purge Loadl/Commit
Page 57 and 58: instructions, because of the lack o
Page 59 and 60: CRF-Relaxed-Commit Rule Site(sache,
Page 61 and 62: 3.4 Universality of the CRF Model M
Page 63 and 64: Translation from CRF to PSO: The Fe
Page 65 and 66: proc proc proc pmb mpb pmb mpb pmb
Page 67 and 68: Chapter 4 The Base Cache Coherence
Page 69 and 70: can be classi ed into two non-overl
Page 71 and 72: arbitrarily in an outgoing queue (t
Page 73 and 74: 4.3 The Imperative Rules of the Bas
Page 75 and 76: Imperative Processor Rules Instruct
Page 77 and 78: Figure 4.5 de nes the rules of the
Page 79 and 80: 4.5.2 Mapping from Base to CRF We d
Page 81 and 82: Base Imperative Rule CRF Rule IP1 (
Page 83 and 84: Base Rule Base Imperative Rule P1 I
Page 85 and 86: eceives a CacheReq message, it will
Page 87 and 88: e completed if it has an in nite nu
Page 89 and 90: SYS Sys(MSITE, SITEs) System MSITE
Page 91 and 92: Commit/Reconcile C-Receive-WbAck Ru
Page 93 and 94: message can be resumed eventually.
Page 95 and 96: If the memory state shows that the
Page 97 and 98: 5.3.3 FIFO Message Passing The live
Page 99 and 100: Figure 5.7 gives the M-engine rules
Page 101 and 102:
Backward-Message-Cache-to-Mem-for-W
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5.4.3 Simulation of WP in CRF Theor
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WP Imperative Rule CRF Rules IP1 (L
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WP Rule WP Imperative & Directive R
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(4) Msg(H,id ,Cache,a,-)" 2 Cin id(
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This completes the proof according
Page 113 and 114:
emains as CachePending, there mustb
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M-engine Rules Msg from id Mstate A
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Chapter 6 The Migratory Cache Coher
Page 119 and 120:
Commit/Reconcile Send Purge Loadl/C
Page 121 and 122:
Mandatory Processor Rules Instructi
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while the memory sends a FlushReq m
Page 125 and 126:
Lemma 38 D is strongly terminating
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Migratory Imperative Rule CRF Rules
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Cell(a,v,C[id ]) 2 Mem(s) _ Cell(a,
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According to Theorem-C and Lemma 45
Page 133 and 134:
CacheReq message. In the latter cas
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Chapter 7 Cachet: A Seamless Integr
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7.1.1 Putting Things Together It is
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Writeback Operations In Cachet, a w
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Composite Message Equivalent Sequen
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Imperative Processor Rules Instruct
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Invalid Commit/Reconcile Receive Ca
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Composite Imperative C-engine Rules
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7.4 The Cachet Cache Coherence Prot
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Voluntary C-engine Rules Cstate Act
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The memory processes an incoming Ca
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The inaccuracy of memory states can
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C-engine Rule of Cachet Deriving Im
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Composite Mandatory Processor Rules
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memory regions simultaneously. In a
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Chapter 8 Conclusions This thesis h
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and heuristic policies. Mandatory r
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technique can be used to allow a ca
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Voluntary C-engine Rules Cstate Act
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FIFO Message Passing msg1 msg2 msg2
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[13] J. K. Archibald. The Cache Coh
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[41] A. Erlichson, N. Nuckolls, G.
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[71] J. Kuskin, D. Ofelt, M. Heinri
Page 179 and 180:
[101] F. Pong and M. Dubois. A New
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