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PreFenceR(a) Fencerr( ,a) Fencewr( ,a) PreFenceW(a) Fencerw( ,a) Fenceww( ,a) PostFenceR(a) Fencerr(a, ) Fencerw(a, ) PostFenceW(a) Fencewr(a, ) Fenceww(a, ) Informally, PreFenceW(a) requires that all preceding Loadl and Commit instructions be completed before any following Storel instruction to location a can be performed. PostFenceR(a) requires that all preceding Loadl instructions to location a be completed before any following Reconcile or Storel instruction can be performed. In an implementation of release consistency, we can use a PreFenceW instruction before releasing a semaphore, and a PostFenceR instruction after acquiring a semaphore. CRF-bits The Loadl and Storel instructions can be augmented with proper CRF-bits so that the semantics of some commit, reconcile and fence operations can be represented without explicit instructions. There are six CRF-bits, Com, Rec, PreR, PreW, PostR and PostW. If turned on, the Com-bit implies a commit operation for a Storel, while a Rec-bit implies a reconcile operation for a Loadl. The PreR, PreW, PostR and PostW bits can be used to enforce fence operations between an address and the whole address space. Intuitively, the PreR-bit means that all preceding Loadl instructions must complete before the instruction itself completes while the PreW-bit means that all preceding Commit instructions must complete before the instruction itself completes. For a Loadl instruction, it makes little sense to set the PreR-bit or PreW-bit without setting the Rec-bit. The PostR-bit implies that the instruction must complete before any following Reconcile instruction completes while the PostW-bit implies that the instruction must complete before any following Storel instruction completes. For a Storel instruction, it makes little sense to set the PostR-bit or PostW-bit without setting the Com-bit. The precise semantics of the CRF-bits can be given using CRF instructions. For example, an instruction with all the CRF- bits set can be de ned as follows: Loadl(a) [Rec,PreR,PreW,PostR,PostW] Fencerr( ,a) Fencewr( ,a) Reconcile(a) Loadl(a) Fencerr(a, ) Fencerw(a, ) Storel(a,v) [Com,PreR,PreW,PostR,PostW] Fencerw( ,a) Fenceww( ,a) Storel(a,v) Commit(a) Fencewr(a, ) Fenceww(a, ) While ne-grain commit and reconcile instructions give the compiler more control over coherence actions of the system, coarse-grain fence instructions can reduce the number of instructions to be executed. In practice, commit and reconcile instructions can also be merged with fence instructions under certain circumstances. Furthermore, the semantics of some CRF instructions can be attached to synchronization instructions such asTest-&-Set and Swap. 58
3.4 Universality of the CRF Model Most relaxed or weaker memory models have arisen as a consequence of speci c architectural optimizations in the implementation of memory access instructions, rather than from some high-level design. Di erent manufacturers have di erent memory models even the same man- ufacturer can have di erent memory models for di erent generations of machines. The CRF model can be used to eliminate the modele de l'annee aspect of many existing memory models. Programs written under sequential consistency and various weaker memory models can be translated into CRF programs without incurring unnecessary overhead. The translations can be taken as precise de nitions of the often imprecise descriptions of the semantics of memory instructions given by the manufacturers. On the other hand, CRF programs can be mapped back to programs that can run e ciently on existing microprocessors. This section demonstrates the upward and downward compatibility of the CRF model. The upward compatibility refersto the the ability to run existing programs correctly and e ciently on a CRF machine. As an example, we show translation schemes for SC, Sparc's TSO, PSO and RMO models and the IBM 370's model. Weaker memory models that allow memory instructions to be reordered usually provide memory barrier or fence instructions that can be used to enforce necessary ordering. Some machines such as IBM 370 have no explicit barrier instructions but instead rely on the implicit barrier-like semantics of some special instructions. We still refer to such instructions as memory barriers (Membar) in the translation schemes. The translation from SC to CRF is simple because SC requires strict in-order and atomic execution of load and store instructions. Loadsc(a) Fencerr( ,a) Fencewr( ,a) Reconcile(a) Loadl(a) Storesc(a,v) Fencerw( ,a) Fenceww( ,a) Storel(a,v) Commit(a) The translation guarantees that the resulting CRF program has exactly the same behavior as the SC program. Note that each fence can be replaced by a coarse-grain instruction Fence( , ) without eliminating any program behavior. TSO allows a load to be performed before outstanding stores complete, which virtually models FIFO write-bu ers. It also allows a load to retrieve the data from an outstanding store to the same address before the data is observable to other processors. Loadtso(a) Fencerr( ,a) Reconcile(a) Loadl(a) Storetso(a,v) Fencerw( ,a) Fenceww( ,a) Storel(a,v) Commit(a) Membar-liketso Fencewr( , ) The translation places a Fencerr before each Reconcile-Loadl pair to ensure the load-load ordering, and a Fencerw and a Fenceww before each Storel-Commit pair to ensure the load-store and store-store ordering. The Membar instruction is simply translated into a write-read fence for all the addresses. PSO allows a load to overtake outstanding stores and in addition, a store to overtake other outstanding stores. This models non-FIFO write bu ers. The short-circuiting is 59
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CSAIL Computer Science and Artifici
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Design and Veri cation of Adaptive
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I am truly grateful to my parents f
Page 10 and 11: 4 The Base Cache Coherence Protocol
Page 13 and 14: List of Figures 1.1 Impact of Archi
Page 15 and 16: Chapter 1 Introduction Shared memor
Page 17 and 18: transparent and exposed only for lo
Page 19 and 20: Example 1: Can both registers r1 an
Page 21 and 22: and release locks, which guard ever
Page 23 and 24: that are interconnected with an o -
Page 25 and 26: although various techniques have be
Page 27 and 28: y showing that each processor can a
Page 29 and 30: s1 if p (s1) ! s2 where s1 and s2 a
Page 31 and 32: Program counter (pc) +1 Instruction
Page 33 and 34: Branch target buffer (btb) Program
Page 35 and 36: instruction is waiting to be dispat
Page 37 and 38: Current State: Proc(ia, rf , rob, b
Page 39 and 40: Rule Name mem pmb mpb Next mem Next
Page 41 and 42: Specification Implementation t 1 B
Page 43 and 44: Intuitively, \2P " means that \P is
Page 45 and 46: (a) (b) PC 1005 PC 2000 Instruction
Page 47 and 48: ewritten to s2 according to rule R.
Page 49 and 50: It can be shown that the relaxed di
Page 51 and 52: Chapter 3 The Commit-Reconcile & Fe
Page 53 and 54: Producer Storel(a,v) Commit(a) Cons
Page 55 and 56: Commit/Reconcile Purge Loadl/Commit
Page 57 and 58: instructions, because of the lack o
Page 59: CRF-Relaxed-Commit Rule Site(sache,
Page 63 and 64: Translation from CRF to PSO: The Fe
Page 65 and 66: proc proc proc pmb mpb pmb mpb pmb
Page 67 and 68: Chapter 4 The Base Cache Coherence
Page 69 and 70: can be classi ed into two non-overl
Page 71 and 72: arbitrarily in an outgoing queue (t
Page 73 and 74: 4.3 The Imperative Rules of the Bas
Page 75 and 76: Imperative Processor Rules Instruct
Page 77 and 78: Figure 4.5 de nes the rules of the
Page 79 and 80: 4.5.2 Mapping from Base to CRF We d
Page 81 and 82: Base Imperative Rule CRF Rule IP1 (
Page 83 and 84: Base Rule Base Imperative Rule P1 I
Page 85 and 86: eceives a CacheReq message, it will
Page 87 and 88: e completed if it has an in nite nu
Page 89 and 90: SYS Sys(MSITE, SITEs) System MSITE
Page 91 and 92: Commit/Reconcile C-Receive-WbAck Ru
Page 93 and 94: message can be resumed eventually.
Page 95 and 96: If the memory state shows that the
Page 97 and 98: 5.3.3 FIFO Message Passing The live
Page 99 and 100: Figure 5.7 gives the M-engine rules
Page 101 and 102: Backward-Message-Cache-to-Mem-for-W
Page 103 and 104: 5.4.3 Simulation of WP in CRF Theor
Page 105 and 106: WP Imperative Rule CRF Rules IP1 (L
Page 107 and 108: WP Rule WP Imperative & Directive R
Page 109 and 110: (4) Msg(H,id ,Cache,a,-)" 2 Cin id(
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This completes the proof according
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emains as CachePending, there mustb
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M-engine Rules Msg from id Mstate A
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Chapter 6 The Migratory Cache Coher
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Commit/Reconcile Send Purge Loadl/C
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Mandatory Processor Rules Instructi
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while the memory sends a FlushReq m
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Lemma 38 D is strongly terminating
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Migratory Imperative Rule CRF Rules
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Cell(a,v,C[id ]) 2 Mem(s) _ Cell(a,
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According to Theorem-C and Lemma 45
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CacheReq message. In the latter cas
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Chapter 7 Cachet: A Seamless Integr
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7.1.1 Putting Things Together It is
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Writeback Operations In Cachet, a w
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Composite Message Equivalent Sequen
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Imperative Processor Rules Instruct
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Invalid Commit/Reconcile Receive Ca
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Composite Imperative C-engine Rules
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7.4 The Cachet Cache Coherence Prot
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Voluntary C-engine Rules Cstate Act
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The memory processes an incoming Ca
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The inaccuracy of memory states can
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C-engine Rule of Cachet Deriving Im
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Composite Mandatory Processor Rules
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memory regions simultaneously. In a
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Chapter 8 Conclusions This thesis h
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and heuristic policies. Mandatory r
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technique can be used to allow a ca
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Voluntary C-engine Rules Cstate Act
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FIFO Message Passing msg1 msg2 msg2
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[13] J. K. Archibald. The Cache Coh
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[41] A. Erlichson, N. Nuckolls, G.
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[71] J. Kuskin, D. Ofelt, M. Heinri
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[101] F. Pong and M. Dubois. A New
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Design and Verification of Adaptive Cache Coherence Protocols ...

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