Design and Verification of Adaptive Cache Coherence Protocols ...

Non-FIFO write bu ers: Some architectures with write bu ers assume that store instruc-
tions can be reordered in a write bu er. This allows stores to the same cache line to be merged
into one burst bus transactions.
Sys(proc, pmb1ht,Store(a,v)ipmb2, mpb, mem) if Load, Store(a,-) =2 pmb1
! Sys(proc, pmb1pmb2, mpbjht,Acki, mem[a:=v])
Non-blocking caches: Modern architectures often have non-blocking caches to allow multi-
ple outstanding load instructions. This e ectively allows loads to be performed out-of-order.
Sys(proc, pmb1ht,Load(a)ipmb2, mpb, mem) if Store =2 pmb1
! Sys(proc, pmb1pmb2, mpbjht,mem[a]i, mem)
A relaxed implementation of memory operations allows memory accesses to be performed in
arbitrary order, provided that data dependences of the program are preserved. A load instruc-
tion can be performed if there is no preceding store instruction on the same address. A store
instruction can be performed if there is no preceding load or store instruction on the same
address. The short-circuit rule allows a load to obtain the data from a preceding store before
the data is written to the memory.
Relaxed-Load-Memory Rule
Sys(proc, pmb1ht,Load(a)ipmb2, mpb, mem) if Store(a,-) =2 pmb1
! Sys(proc, pmb1pmb2, mpbjht,mem[a]i, mem)
Relaxed-Store-Memory Rule
Sys(proc, pmb1ht,Store(a,v)ipmb2, mpb, mem) if Load(a), Store(a,-) =2 pmb1
! Sys(proc, pmb1pmb2, mpbjht,Acki, mem[a:=v])
Short-Circuit Rule
Sys(proc, pmb1ht 0 ,Store(a,v)ipmb2ht,Load(a)ipmb3, mpb, mem) if Store(a,-) =2 pmb2
! Sys(proc, pmb1ht 0 ,Store(a,v)ipmb2pmb3, mpbjht,vi, mem)
We can use the relaxed memory access rules above as a more e cient processor-memory
interface for PS (this inevitably leads to a relaxed memory model in multiprocessor systems). We
can further allow memory instructions to be dispatched out-of-order (t 0 represents an unresolved
tag):
Relaxed-Dispatch-Load Rule
Sys(Proc(ia, rf , rob1 Itb(ia1,t :=Load(a,U),Wr(r)) rob2, btb, im), pmb, mpb, mem)
if Jz, Load(t 0 ,U), Store(-,t 0 ,U), Store(t 0 ,-,U) Store(a,-,U) =2 rob1
! Sys(Proc(ia, rf , rob1 Itb(ia1,t :=Load(a,D),Wr(r)) rob2, btb, im), pmbht,Load(a)i, mpb,
mem)
Relaxed-Dispatch-Store Rule
Sys(Proc(ia, rf , rob1 Itb(ia1,t :=Store(a,v,U)) rob2, btb, im), pmb, mpb, mem)
if Jz, Load(t 0 ,U), Store(-,t 0 ,U), Store(t 0 ,-,U) Load(a,U), Store(a,-,U) =2 rob1
! Sys(Proc(ia, rf , rob1 Itb(ia1,t :=Store(a,v,D)) rob2, btb, im), pmbht,Store(a,v)i, mpb, mem)
46