Design and Verification of Adaptive Cache Coherence Protocols ...

Lemma 34 Given a WP sequence ,
(1) Loadl(a) 2 Pmb id( ) Loadl(a) 2 Pmb id( ) ^
(Cell(a,-,Clean) 2 Cache id( ) _ Cell(a,-,Dirty) 2 Cache id( ))
(2) Storel(a,-) 2 Pmb id( ) Storel(a,-) 2 Pmb id( ) ^
(Cell(a,-,Clean) 2 Cache id( ) _ Cell(a,-,Dirty) 2 Cache id( ))
(3) Commit(a) 2 Pmb id( ) Commit(a) 2 Pmb id ( ) ^
(Cell(a,-,Clean) 2 Cache id( ) _ a =2 Cache id( ))
(4) Reconcile(a) 2 Pmb id( ) Reconcile(a) 2 Pmb id( ) ^
(Cell(a,-,Clean) 2 Cache id( ) _ Cell(a,-,Dirty) 2 Cache id( ) _ a =2 Cache id( ))
Proof We rst show that when a processor intends to execute an instruction, the cache cell
will be set to an appropriate state. This can be represented by the following proposition the
proof follows from Lemmas 27, 32 and 33.
Loadl(a) 2 Pmb id( ) Cell(a,-,Clean) 2 Cache id( ) _ Cell(a,-,Dirty) 2 Cache id( )
Storel(a,-) 2 Pmb id( ) Cell(a,-,Clean) 2 Cache id( ) _ Cell(a,-,Dirty) 2 Cache id( )
Commit(a) 2 Pmb id ( ) Cell(a,-,Clean) 2 Cache id( ) _ a =2 Cache id( )
Reconcile(a) 2 Pmb id( )
Cell(a,-,Clean) 2 Cache id( ) _ Cell(a,-,Dirty) 2 Cache id( ) _ a =2 Cache id( )
We then show that an instruction can be completed only when the address is cached in an
appropriate state. This can be represented by the following proposition, which can be veri ed
by simplychecking the WP rules that allow an instruction to be retired.
ht,Loadl(a)i2Pmb id( ) ^ ht,Loadl(a)i =2 Pmb id( )
) Cell(a,-,Clean) 2 Cache id( ) _ Cell(a,-,Dirty) 2 Cache id( )
ht,Storel(a,-)i2Pmb id( ) ^ ht,Storel(a,-)i =2 Pmb id( )
) Cell(a,-,Clean) 2 Cache id( ) _ Cell(a,-,Dirty) 2 Cache id( )
ht,Commit(a)i2Pmb id ( ) ^ ht,Commit(a)i =2 Pmb id( )
) Cell(a,-,Clean) 2 Cache id( ) _ a =2 Cache id( )
ht,Reconcile(a)i2Pmb id( ) ^ ht,Reconcile(a)i =2 Pmb id( )
) Cell(a,-,Clean) 2 Cache id( ) _ Cell(a,-,Dirty) 2 Cache id( ) _ a =2 Cache id( )
This completes the proof according to Theorem-B. 2
The liveness of WP ensures that a memory instruction can always be completed eventually.
This is described by the following theorem, which trivially follows from Lemma 34. Note that
Rules P1, P2, P6, P7, P11, P15, P16, P17 and P20 are strongly fair.
Theorem 35 (Liveness of WP) Given a WP sequence ,
(1) ht,Loadl(-)i2Pmb id( ) ht,-i2Mpb id ( )
(2) ht,Storel(-,-)i2Pmb id( ) ht,Acki2Mpb id ( )
(3) ht,Commit(-)i2Pmb id( ) ht,Acki2Mpb id ( )
(4) ht,Reconcile(-)i2Pmb id( ) ht,Acki2Mpb id ( )
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