Design and Verification of Adaptive Cache Coherence Protocols ...

4.6.2 Liveness of Base
Lemma 13 ensures that whenever a processor intends to execute an instruction, the cache cell
will be set to an appropriate state while the instruction remains in the processor-to-memory
bu er. For a Loadl or Storel, the cache state will be set to Clean or Dirty for a Commit, the
cache state will be set to Clean or Invalid for a Reconcile, the cache state will be set to Dirty
or Invalid.
Lemma 13 Given a Base sequence ,
(1) Loadl(a) 2 Pmb id( ) Loadl(a) 2 Pmb id( ) ^
(Cell(a,-,Clean) 2 Cache id( ) _ Cell(a,-,Dirty) 2 Cache id( ))
(2) Storel(a,-) 2 Pmb id( ) Storel(a,-) 2 Pmb id( ) ^
(Cell(a,-,Clean) 2 Cache id( ) _ Cell(a,-,Dirty) 2 Cache id( ))
(3) Commit(a) 2 Pmb id( ) Commit(a) 2 Pmb id ( ) ^
(Cell(a,-,Clean) 2 Cache id( ) _ a =2 Cache id( ))
(4) Reconcile(a) 2 Pmb id( ) Reconcile(a) 2 Pmb id( ) ^
(Cell(a,-,Dirty) 2 Cache id( ) _ a =2 Cache id( ))
Proof We rst show that when a processor intends to execute an instruction, the cache cell
will be brought to an appropriate state. This can be represented by the following proposition
the proof follows from Lemmas 11 and 12.
Loadl(a) 2 Pmb id( ) Cell(a,-,Clean) 2 Cache id( ) _ Cell(a,-,Dirty) 2 Cache id( )
Storel(a,-) 2 Pmb id( ) Cell(a,-,Clean) 2 Cache id( ) _ Cell(a,-,Dirty) 2 Cache id( )
Commit(a) 2 Pmb id ( ) Cell(a,-,Clean) 2 Cache id( ) _ a =2 Cache id( )
Reconcile(a) 2 Pmb id( ) Cell(a,-,Dirty) 2 Cache id( ) _ a =2 Cache id( )
We then show that an instruction can be completed only when the address is cached in an
appropriate state. This can be represented by the following proposition, which can be veri ed
by simplychecking each Base rule.
ht,Loadl(a)i2Pmb id( ) ^ ht,Loadl(a)i =2 Pmb id( )
) Cell(a,-,Clean) 2 Cache id( ) _ Cell(a,-,Dirty) 2 Cache id( )
ht,Storel(a,-)i2Pmb id( ) ^ ht,Storel(a,-)i =2 Pmb id( )
) Cell(a,-,Clean) 2 Cache id( ) _ Cell(a,-,Dirty) 2 Cache id( )
ht,Commit(a)i2Pmb id ( ) ^ ht,Commit(a)i =2 Pmb id( )
) Cell(a,-,Clean) 2 Cache id( ) _ a =2 Cache id( )
ht,Reconcile(a)i2Pmb id( ) ^ ht,Reconcile(a)i =2 Pmb id( )
) Cell(a,-,Dirty) 2 Cache id( ) _ a =2 Cache id( )
This completes the proof according to Theorem-B (see Section 2.5). 2
Lemma 13 ensures that when a processor intends to execute an instruction, the cache cell will be
brought into an appropriate state so that the instruction can be completed. However, this does
not guarantee that the instruction will be completed since a cache state can change at any time
because of voluntary rules. To ensure that each processor makes progress, an instruction must
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