Design and Verification of Adaptive Cache Coherence Protocols ...

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Migratory Rule Migratory Imperative & Directive Rules P1 Loadl-on-Clean P2 Loadl-on-Dirty P3 P4 C-Send-CacheReq P5 Storel-on-Clean P6 Storel-on-Dirty P7 P8 C-Send-CacheReq P9 Commit-on-Clean P10 Commit-on-Dirty P11 P12 Commit-on-Invalid P13 Reconcile-on-Clean P14 Reconcile-on-Dirty P15 P16 Reconcile-on-Invalid VC1 C-Send-Flush VC2 C-Send-Purge VC3 C-Send-CacheReq MC1 C-Receive-Cache MC2 C-Receive-Cache MC3 C-Receive-FlushReq + C-Send-Purge MC4 C-Receive-FlushReq + C-Send-Flush MC5 C-Receive-FlushReq MC6 C-Receive-FlushReq VM1 M-Send-Cache VM2 M-Send-FlushReq MM1 M-Receive-CacheReq + M-Send-Cache MM2 M-Send-FlushReq MM3 M-Receive-CacheReq MM4 MM5 M-Receive-CacheReq MM6 M-Receive-Purge MM7 M-Receive-Purge MM8 M-Receive-Flush MM9 M-Receive-Flush Figure 6.7: Derivation of Migratory from Imperative & Directive Rules 6.5 Liveness Proof of the Migratory Protocol We prove the liveness of Migratory by showing that each processor can always make progress. We assume FIFO message passing and proper bu er management as described in Section 6.3. The lemmas and theorems in this section are given in the context of the integrated rules of Migratory. 6.5.1 Some Invariants of Migratory Lemma 44 is the same as Lemma 36, except that the C[id ] state of the imperative rules is replaced by the C[id ] and T[id ] states of the integrated rules. Lemma 44 Given a Migratory term s, 126
Cell(a,v,C[id ]) 2 Mem(s) _ Cell(a,v,T[id ]) 2 Mem(s) , Cell(a,v,Clean) 2 Cache id(s) _ Cell(a,-,Dirty) 2 Cache id(s) _ Msg(H,id ,Cache,a,v) 2 MoutCin id (s) _ Msg(id ,H,Purge,a) 2 MinCout id(s) _ Msg(id ,H,Flush,a,-) 2 MinCout id (s) Lemma 45 includes invariants regarding message generation and processing. Invariants (1)-(2) ensure that when a Loadl or Storel instruction is performed on an uncached address, the cache will eventually contain a clean cell for the accessed address, or issue a CacheReq message and set the cache state to CachePending. The proof follows from the weak fairness of Rules P4 and P8. Invariants (3)-(5) ensure that when a cache receives a Cache message, it will cache the data in the Clean state when a cache receives a FlushReq message, if the address is cached in the Clean or Dirty state, the cache will send a Purge or Flush message to the memory. The proof follows from the weak fairness of Rules MC1, MC2, MC3 and MC4. Invariants (6)-(7) ensure that when the memory receives a Purge or Flush message, it will set the memory state to C[ ]. The proof follows from the weak fairness of Rules MM6, MM7, MM8 and MM9. Invariants (8)-(9) ensure that each outgoing message will be delivered to its destination's incoming queue. This can be proved by induction on the number of preceding messages in the outgoing queue (note that the message passing rules are weakly fair). Lemma 45 Given a Migratory sequence , (1) ht,Loadl(a)i2Pmb id( ) ^ a =2 Cache id( ) Cell(a,-,Clean) 2 Cache id( ) _ (Cell(a,-,CachePending) 2 Cache id( ) ^ Msg(id ,H,CacheReq,a) 2 Cout id ( )) (2) ht,Storel(a,-)i2Pmb id( ) ^ a =2 Cache id( ) Cell(a,-,Clean) 2 Cache id( ) _ (Cell(a,-,CachePending) 2 Cache id( ) ^ Msg(id ,H,CacheReq,a) 2 Cout id ( )) (3) Msg(H,id ,Cache,a,-)" 2 Cin id( ) Cell(a,-,Clean) 2 Cache id( ) (4) Msg(H,id ,FlushReq,a)" 2 Cin id ( ) ^ Cell(a,-,Clean) 2 Cache id( ) Msg(id ,H,Purge,a) 2 Cout id( ) (5) Msg(H,id ,FlushReq,a)" 2 Cin id ( ) ^ Cell(a,-,Dirty) 2 Cache id( ) Msg(id ,H,Flush,a,-) 2 Cout id ( ) (6) Msg(id ,H,Flush,a,-)" 2 Min( ) Cell(a,-,C[ ]) 2 Mem( ) (7) Msg(id ,H,Purge,a)" 2 Min( ) Cell(a,-,C[ ]) 2 Mem( ) (8) msg 2 Cout id( ) ^ Dest(msg)=H msg 2 Min( ) (9) msg 2 Mout( ) ^ Dest(msg)=id msg 2 Cin id( ) Lemma 46 ensures that an incoming Cache, FlushReq, Purge or Flush message will eventually become the rst message regarding the address in the incoming queue. Therefore, the message will be brought to the front end of the incoming queue sooner or later so that it can be processed. This lemma is a special case of Lemma 48. 127
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CSAIL Computer Science and Artifici
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Design and Veri cation of Adaptive
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I am truly grateful to my parents f
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4 The Base Cache Coherence Protocol
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List of Figures 1.1 Impact of Archi
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Chapter 1 Introduction Shared memor
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transparent and exposed only for lo
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Example 1: Can both registers r1 an
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and release locks, which guard ever
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that are interconnected with an o -
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although various techniques have be
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y showing that each processor can a
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s1 if p (s1) ! s2 where s1 and s2 a
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Program counter (pc) +1 Instruction
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Branch target buffer (btb) Program
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instruction is waiting to be dispat
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Current State: Proc(ia, rf , rob, b
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Rule Name mem pmb mpb Next mem Next
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Specification Implementation t 1 B
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Intuitively, \2P " means that \P is
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(a) (b) PC 1005 PC 2000 Instruction
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ewritten to s2 according to rule R.
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It can be shown that the relaxed di
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Chapter 3 The Commit-Reconcile & Fe
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Producer Storel(a,v) Commit(a) Cons
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Commit/Reconcile Purge Loadl/Commit
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instructions, because of the lack o
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CRF-Relaxed-Commit Rule Site(sache,
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3.4 Universality of the CRF Model M
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Translation from CRF to PSO: The Fe
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proc proc proc pmb mpb pmb mpb pmb
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Chapter 4 The Base Cache Coherence
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can be classi ed into two non-overl
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arbitrarily in an outgoing queue (t
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4.3 The Imperative Rules of the Bas
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Imperative Processor Rules Instruct
Page 77 and 78: Figure 4.5 de nes the rules of the
Page 79 and 80: 4.5.2 Mapping from Base to CRF We d
Page 81 and 82: Base Imperative Rule CRF Rule IP1 (
Page 83 and 84: Base Rule Base Imperative Rule P1 I
Page 85 and 86: eceives a CacheReq message, it will
Page 87 and 88: e completed if it has an in nite nu
Page 89 and 90: SYS Sys(MSITE, SITEs) System MSITE
Page 91 and 92: Commit/Reconcile C-Receive-WbAck Ru
Page 93 and 94: message can be resumed eventually.
Page 95 and 96: If the memory state shows that the
Page 97 and 98: 5.3.3 FIFO Message Passing The live
Page 99 and 100: Figure 5.7 gives the M-engine rules
Page 101 and 102: Backward-Message-Cache-to-Mem-for-W
Page 103 and 104: 5.4.3 Simulation of WP in CRF Theor
Page 105 and 106: WP Imperative Rule CRF Rules IP1 (L
Page 107 and 108: WP Rule WP Imperative & Directive R
Page 109 and 110: (4) Msg(H,id ,Cache,a,-)" 2 Cin id(
Page 111 and 112: This completes the proof according
Page 113 and 114: emains as CachePending, there mustb
Page 115 and 116: M-engine Rules Msg from id Mstate A
Page 117 and 118: Chapter 6 The Migratory Cache Coher
Page 119 and 120: Commit/Reconcile Send Purge Loadl/C
Page 121 and 122: Mandatory Processor Rules Instructi
Page 123 and 124: while the memory sends a FlushReq m
Page 125 and 126: Lemma 38 D is strongly terminating
Page 127: Migratory Imperative Rule CRF Rules
Page 131 and 132: According to Theorem-C and Lemma 45
Page 133 and 134: CacheReq message. In the latter cas
Page 135 and 136: Chapter 7 Cachet: A Seamless Integr
Page 137 and 138: 7.1.1 Putting Things Together It is
Page 139 and 140: Writeback Operations In Cachet, a w
Page 141 and 142: Composite Message Equivalent Sequen
Page 143 and 144: Imperative Processor Rules Instruct
Page 145 and 146: Invalid Commit/Reconcile Receive Ca
Page 147 and 148: Composite Imperative C-engine Rules
Page 149 and 150: 7.4 The Cachet Cache Coherence Prot
Page 151 and 152: Voluntary C-engine Rules Cstate Act
Page 153 and 154: The memory processes an incoming Ca
Page 155 and 156: The inaccuracy of memory states can
Page 157 and 158: C-engine Rule of Cachet Deriving Im
Page 159 and 160: Composite Mandatory Processor Rules
Page 161 and 162: memory regions simultaneously. In a
Page 163 and 164: Chapter 8 Conclusions This thesis h
Page 165 and 166: and heuristic policies. Mandatory r
Page 167 and 168: technique can be used to allow a ca
Page 169 and 170: Voluntary C-engine Rules Cstate Act
Page 171 and 172: FIFO Message Passing msg1 msg2 msg2
Page 173 and 174: [13] J. K. Archibald. The Cache Coh
Page 175 and 176: [41] A. Erlichson, N. Nuckolls, G.
Page 177 and 178: [71] J. Kuskin, D. Ofelt, M. Heinri
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[101] F. Pong and M. Dubois. A New
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