Design and Verification of Adaptive Cache Coherence Protocols ...

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Imperative C-engine Rules Msg from H Cstate Action Next Cstate Cell(a,-,Cleanb) a =2 cache IC1 Cell(a,v,Dirtyb) hWbb,a,vi!H Cell(a,v,WbPending) IC2 Cell(a,v,Cleanw) hDownwb,ai!H Cell(a,v,Cleanb) IC3 Cell(a,v,Dirtyw) hDownwb,ai!H Cell(a,v,Dirtyb) IC4 Cell(a,v,Cleanm) hDownmw,ai!H Cell(a,v,Cleanw) IC5 Cell(a,v,Dirtym) hDownVmw,a,vi!H Cell(a,v,Cleanw) IC6 a =2 cache hCacheReq,ai !H Cell(a,-,CachePending) IC7 hCacheb,a,vi Cell(a,-,CachePending) Cell(a,v,Cleanb) IC8 hCachew,a,vi Cell(a,-,Cleanb) Cell(a,v,Cleanw) IC9 Cell(a,v1,Dirtyb) Cell(a,v1,Dirtyw) IC10 Cell(a,v1,WbPending) Cell(a,v1,WbPending) IC11 Cell(a,-,CachePending) Cell(a,v,Cleanw) IC12 a =2 cache Cell(a,v,Cleanw) IC13 hUpwm,ai Cell(a,v,Cleanb) Cell(a,v,Cleanb) IC14 Cell(a,v,Dirtyb) Cell(a,v,Dirtyb) IC15 Cell(a,v,Cleanw) Cell(a,v,Cleanm) IC16 Cell(a,v,Dirtyw) Cell(a,v,Dirtym) IC17 Cell(a,v,WbPending) Cell(a,v,WbPending) IC18 Cell(a,-,CachePending) Cell(a,-,CachePending) IC19 a =2 cache a =2 cache IC20 hWbAckb,ai Cell(a,v,WbPending) Cell(a,v,Cleanb) IC21 hWbAckw,ai Cell(a,v,WbPending) Cell(a,v,Cleanw) IC22 Figure 7.6: Imperative Cache Engine Rules of Cachet data of the Base cell back to the memory before it receives the Cachew message. If a cache receives a Cachew message for an uncached address, or an address cached in the CachePending state , it caches the data in the Clean state of WP (Rules IC12 and IC13). If a cache receives an Upwm message for a Base cell, it discards the message (Rules IC14 and IC15). This can happen because the cache can voluntarily downgrade a WP cell while the memory intends to upgrade the cache cell. If a cache receives an Upwm message for a WP cell, it upgrades the cache cell to Migratory (Rules 16 and 17). If a cache receives an Upwm message for an uncached address, or an address cached in the WbPending or CachePending state, it discards the message (Rules IC18, IC19 and IC20). This can happen if the cache has downgraded the cell from WP to Base before it receives the upgrade message, and the Base cell has been purged from the cache or written back to the memory. Figure 7.7 shows the cache state transitions of Cachet due to imperative operations (composite operations are not shown). 7.3.3 Imperative Memory Engine Rules Figure 7.8 gives the set of imperative M-engine rules of Cachet. When the memory engine receives a message, it removes the message from the incoming queue. If the memory state shows that an address is not resident inacache, the memory can send aCachew message to supply a WP copy to the cache (Rule IM1). The cache may contain 142
Invalid Commit/Reconcile Receive Cachew Receive Cachew Send Downmw Loadl/Commit/Reconcile Loadl/Commit/Reconcile Loadl/Storel/Commit/Reconcile Clean Dirty m m Receive Up wm Send Downmb Storel Send DownVmw Clean Dirty w w Receive WbAckw Send Downmb Send CacheReq Receive Cacheb Receive WbAckb Send Wb b Cache- Pending Cleanb Wb- Pending Dirtyb Purge Receive Up wm Storel Loadl/Storel/Reconcile Receive Cachew Loadl/Commit Storel Loadl/Storel/Reconcile Figure 7.7: Cache State Transitions of Cachet a Base cell, since the memory maintains no information for addresses cached under Base. In this case, the Cachew message invokes an upgrade operation on the cache cell. If the memory state shows that an address is cached exclusively in a cache under WP, the memory can send an Upwm message to upgrade the cache cell to Migratory (Rule IM2). When the memory receives a CacheReq message, if the memory state shows that the address is uncached in the cache and that the address is uncached in any other cache under Migratory, the memory can send a Cacheb message to supply a Base copy to the cache (Rule IM3). An alternative treatment is to let the memory send a Cachew message to supply a WP copy (Rule IM1) and then discard the cache request (Rule IM4). When the memory receivesaCacheReq message, if the memory state shows that the address is cached in the cache, the memory discards the cache request (Rules IM4 and IM5). This can happen because the memory can voluntarily supply a WP copy toacache the WP cell can be further upgraded to a Migratory cell. When the memory receives a Wbb message, if the memory state shows that the address is uncached in the cache, the memory suspends the writeback message for later processing (Rules IM6 and IM8). When the memory receives a Wbb message, if the memory state shows that the cache contains a WP copy for the address, the memory suspends the writeback message and removes the cache identi er from the corresponding directory (Rule IM7). This can happen if the memory sends a Cachew message to the cache before it receives the Wbb message. The Cachew message will be discarded at the cache (Rule IC11). 143
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CSAIL Computer Science and Artifici
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Design and Veri cation of Adaptive
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I am truly grateful to my parents f
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4 The Base Cache Coherence Protocol
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List of Figures 1.1 Impact of Archi
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Chapter 1 Introduction Shared memor
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transparent and exposed only for lo
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Example 1: Can both registers r1 an
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and release locks, which guard ever
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that are interconnected with an o -
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although various techniques have be
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y showing that each processor can a
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s1 if p (s1) ! s2 where s1 and s2 a
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Program counter (pc) +1 Instruction
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Branch target buffer (btb) Program
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instruction is waiting to be dispat
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Current State: Proc(ia, rf , rob, b
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Rule Name mem pmb mpb Next mem Next
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Specification Implementation t 1 B
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Intuitively, \2P " means that \P is
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(a) (b) PC 1005 PC 2000 Instruction
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ewritten to s2 according to rule R.
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It can be shown that the relaxed di
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Chapter 3 The Commit-Reconcile & Fe
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Producer Storel(a,v) Commit(a) Cons
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Commit/Reconcile Purge Loadl/Commit
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instructions, because of the lack o
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CRF-Relaxed-Commit Rule Site(sache,
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3.4 Universality of the CRF Model M
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Translation from CRF to PSO: The Fe
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proc proc proc pmb mpb pmb mpb pmb
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Chapter 4 The Base Cache Coherence
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can be classi ed into two non-overl
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arbitrarily in an outgoing queue (t
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4.3 The Imperative Rules of the Bas
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Imperative Processor Rules Instruct
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Figure 4.5 de nes the rules of the
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4.5.2 Mapping from Base to CRF We d
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Base Imperative Rule CRF Rule IP1 (
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Base Rule Base Imperative Rule P1 I
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eceives a CacheReq message, it will
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e completed if it has an in nite nu
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SYS Sys(MSITE, SITEs) System MSITE
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Commit/Reconcile C-Receive-WbAck Ru
Page 93 and 94: message can be resumed eventually.
Page 95 and 96: If the memory state shows that the
Page 97 and 98: 5.3.3 FIFO Message Passing The live
Page 99 and 100: Figure 5.7 gives the M-engine rules
Page 101 and 102: Backward-Message-Cache-to-Mem-for-W
Page 103 and 104: 5.4.3 Simulation of WP in CRF Theor
Page 105 and 106: WP Imperative Rule CRF Rules IP1 (L
Page 107 and 108: WP Rule WP Imperative & Directive R
Page 109 and 110: (4) Msg(H,id ,Cache,a,-)" 2 Cin id(
Page 111 and 112: This completes the proof according
Page 113 and 114: emains as CachePending, there mustb
Page 115 and 116: M-engine Rules Msg from id Mstate A
Page 117 and 118: Chapter 6 The Migratory Cache Coher
Page 119 and 120: Commit/Reconcile Send Purge Loadl/C
Page 121 and 122: Mandatory Processor Rules Instructi
Page 123 and 124: while the memory sends a FlushReq m
Page 125 and 126: Lemma 38 D is strongly terminating
Page 127 and 128: Migratory Imperative Rule CRF Rules
Page 129 and 130: Cell(a,v,C[id ]) 2 Mem(s) _ Cell(a,
Page 131 and 132: According to Theorem-C and Lemma 45
Page 133 and 134: CacheReq message. In the latter cas
Page 135 and 136: Chapter 7 Cachet: A Seamless Integr
Page 137 and 138: 7.1.1 Putting Things Together It is
Page 139 and 140: Writeback Operations In Cachet, a w
Page 141 and 142: Composite Message Equivalent Sequen
Page 143: Imperative Processor Rules Instruct
Page 147 and 148: Composite Imperative C-engine Rules
Page 149 and 150: 7.4 The Cachet Cache Coherence Prot
Page 151 and 152: Voluntary C-engine Rules Cstate Act
Page 153 and 154: The memory processes an incoming Ca
Page 155 and 156: The inaccuracy of memory states can
Page 157 and 158: C-engine Rule of Cachet Deriving Im
Page 159 and 160: Composite Mandatory Processor Rules
Page 161 and 162: memory regions simultaneously. In a
Page 163 and 164: Chapter 8 Conclusions This thesis h
Page 165 and 166: and heuristic policies. Mandatory r
Page 167 and 168: technique can be used to allow a ca
Page 169 and 170: Voluntary C-engine Rules Cstate Act
Page 171 and 172: FIFO Message Passing msg1 msg2 msg2
Page 173 and 174: [13] J. K. Archibald. The Cache Coh
Page 175 and 176: [41] A. Erlichson, N. Nuckolls, G.
Page 177 and 178: [71] J. Kuskin, D. Ofelt, M. Heinri
Page 179 and 180: [101] F. Pong and M. Dubois. A New
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