Design and Verification of Adaptive Cache Coherence Protocols ...

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still permitted as in TSO. Loadpso(a) Fencerr( ,a) Reconcile(a) Loadl(a) Storepso(a,v) Fencerw( ,a) Storel(a,v) Commit(a) Membarpso Fencewr( , ) Fenceww( , ) RMO allows memory accesses to be reordered arbitrarily,provided that data dependencies are respected. Loadrmo(a) Reconcile(a) Loadl(a) Storermo(a,v) Storel(a,v) Commit(a) Membar#LoadLoadrmo Fencerr( , ) Membar#LoadStorermo Fencerw( , ) Membar#StoreLoadrmo Fencewr( , ) Membar#StoreStorermo Fenceww( , ) Like TSO, IBM 370 allows the use of write bu ers so that a load can be performed before outstanding stores complete. However, it prohibits data short-circuiting from write bu ers and requires that each load retrieve data directly from the memory. In other words, the data of a store operation cannot be observed byany processor before it becomes observable to all the processors. The translation from IBM 370 to CRF is the same as the translation from TSO to CRF, except for a Fencewr instruction to ensure the ordering between a Store and a following Load to the same address. Load370(a) Fencewr(a,a) Fencerr( ,a) Reconcile(a) Loadl(a) Store370(a,v) Fencerw( ,a) Fenceww( ,a) Storel(a,v) Commit(a) Membar370 Fencewr( , ) Downward compatibility refers to the ability to run CRF programs on existing machines. Many existing systems can be interpreted as speci c implementations of CRF, though more e cient implementations are possible. We showhow CRF programs can be translated into programs that can run on microprocessors that support SC, Sparc's TSO, PSO and RMO models, and IBM 370's model. In all the translation schemes, we translate Loadl and Storel into the load and store instructions of the target machines. Both Commit and Reconcile become Nop's, since the semantics are implied by the corresponding load and store operations. For di erent target machines, the translation schemes di er in dealing with memory fences. A translation avoids employing unnecessary memory barriers by exploiting speci c ordering constraints guaranteed by the underlying architecture. Translation from CRF to SC: All CRF fences simply become Nop's, since memory accesses are executed strictly in-order in SC machines. Translation from CRF to TSO: The Fencerr, Fencerw and Fenceww instructions are translated into Nop's, since TSO implicitly guarantees the load-load, load-store and store-store ordering. The Fencewr instruction is translated into Membar. 60
Translation from CRF to PSO: The Fencerr and Fencerw instructions are translated into Nop's, since PSO implicitly preserves the load-load and load-store ordering. Both Fencewr and Fenceww are translated into Membar. Translation from CRF to RMO: Since RMO assumes no ordering between memory accesses unless explicit memory barriers are inserted, the translation scheme translates each CRF fence into the corresponding RMO memory barrier. Translation from CRF to IBM 370: Since IBM 370's model is slightly stricter than the TSO model, the translation can avoid some memory barriers by taking advantage from the fact that IBM 370 prohibits data short-circuiting from write-bu ers. This suggests that a Fencewr with identical pre-address and post-address be translated into a Nop. We can translate programs based on release consistency to CRF programs by de ning the release and acquire operations using CRF instructions and synchronization instructions such as Lock/Unlock. The synchronization instructions are provided for mutual exclusion, and have no ordering implication on other instructions. In terms of reordering constraints, a Lock can be treated as a Loadl followed by a Storel, and an Unlock can be treated as a Storel. Release(s) Commit( ) PreFenceW(s) Unlock(s) Acquire(s) Lock(s) PostFenceR(s) Reconcile( ) One can think of the translation scheme above as the de nition of one version of release consistency. Obviously, memory accesses after a release can be performed before the semaphore is released, because the release only imposes a pre-fence on preceding accesses. Similarly, memory accesses before an acquire do not have to be completed before the semaphore is acquired, because the acquire only imposes a post-fence on following memory accesses. Furthermore, modi ed data of a store before a release need to be written back to the memory at the release point, but a data copy of the address in another cache does not have to be invalidated or up- dated immediately. This is because the stale data copy, if any, will be reconciled at the next acquire point. 3.5 The Generalized CRF Model In CRF, the memory behaves as the rendezvous of saches. A writeback operation is atomic with respect to all the sites: if a sache can retrieve some data from the memory, another sache must be able to retrieve the same data from the memory at the same time. Therefore, if two stores are observed by more than one processor, they are observed in the same order provided that the loads used in the observation are executed in order. As an example, the following program illustrates that non-atomic store operations can generate surprising behaviors even when only one memory location is involved. Assume initially location a has value 0. Processors A and B modify location a while processors C and D read 61
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CSAIL Computer Science and Artifici
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Design and Veri cation of Adaptive
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I am truly grateful to my parents f
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4 The Base Cache Coherence Protocol
Page 13 and 14: List of Figures 1.1 Impact of Archi
Page 15 and 16: Chapter 1 Introduction Shared memor
Page 17 and 18: transparent and exposed only for lo
Page 19 and 20: Example 1: Can both registers r1 an
Page 21 and 22: and release locks, which guard ever
Page 23 and 24: that are interconnected with an o -
Page 25 and 26: although various techniques have be
Page 27 and 28: y showing that each processor can a
Page 29 and 30: s1 if p (s1) ! s2 where s1 and s2 a
Page 31 and 32: Program counter (pc) +1 Instruction
Page 33 and 34: Branch target buffer (btb) Program
Page 35 and 36: instruction is waiting to be dispat
Page 37 and 38: Current State: Proc(ia, rf , rob, b
Page 39 and 40: Rule Name mem pmb mpb Next mem Next
Page 41 and 42: Specification Implementation t 1 B
Page 43 and 44: Intuitively, \2P " means that \P is
Page 45 and 46: (a) (b) PC 1005 PC 2000 Instruction
Page 47 and 48: ewritten to s2 according to rule R.
Page 49 and 50: It can be shown that the relaxed di
Page 51 and 52: Chapter 3 The Commit-Reconcile & Fe
Page 53 and 54: Producer Storel(a,v) Commit(a) Cons
Page 55 and 56: Commit/Reconcile Purge Loadl/Commit
Page 57 and 58: instructions, because of the lack o
Page 59 and 60: CRF-Relaxed-Commit Rule Site(sache,
Page 61: 3.4 Universality of the CRF Model M
Page 65 and 66: proc proc proc pmb mpb pmb mpb pmb
Page 67 and 68: Chapter 4 The Base Cache Coherence
Page 69 and 70: can be classi ed into two non-overl
Page 71 and 72: arbitrarily in an outgoing queue (t
Page 73 and 74: 4.3 The Imperative Rules of the Bas
Page 75 and 76: Imperative Processor Rules Instruct
Page 77 and 78: Figure 4.5 de nes the rules of the
Page 79 and 80: 4.5.2 Mapping from Base to CRF We d
Page 81 and 82: Base Imperative Rule CRF Rule IP1 (
Page 83 and 84: Base Rule Base Imperative Rule P1 I
Page 85 and 86: eceives a CacheReq message, it will
Page 87 and 88: e completed if it has an in nite nu
Page 89 and 90: SYS Sys(MSITE, SITEs) System MSITE
Page 91 and 92: Commit/Reconcile C-Receive-WbAck Ru
Page 93 and 94: message can be resumed eventually.
Page 95 and 96: If the memory state shows that the
Page 97 and 98: 5.3.3 FIFO Message Passing The live
Page 99 and 100: Figure 5.7 gives the M-engine rules
Page 101 and 102: Backward-Message-Cache-to-Mem-for-W
Page 103 and 104: 5.4.3 Simulation of WP in CRF Theor
Page 105 and 106: WP Imperative Rule CRF Rules IP1 (L
Page 107 and 108: WP Rule WP Imperative & Directive R
Page 109 and 110: (4) Msg(H,id ,Cache,a,-)" 2 Cin id(
Page 111 and 112: This completes the proof according
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emains as CachePending, there mustb
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M-engine Rules Msg from id Mstate A
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Chapter 6 The Migratory Cache Coher
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Commit/Reconcile Send Purge Loadl/C
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Mandatory Processor Rules Instructi
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while the memory sends a FlushReq m
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Lemma 38 D is strongly terminating
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Migratory Imperative Rule CRF Rules
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Cell(a,v,C[id ]) 2 Mem(s) _ Cell(a,
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According to Theorem-C and Lemma 45
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CacheReq message. In the latter cas
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Chapter 7 Cachet: A Seamless Integr
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7.1.1 Putting Things Together It is
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Writeback Operations In Cachet, a w
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Composite Message Equivalent Sequen
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Imperative Processor Rules Instruct
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Invalid Commit/Reconcile Receive Ca
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Composite Imperative C-engine Rules
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7.4 The Cachet Cache Coherence Prot
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Voluntary C-engine Rules Cstate Act
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The memory processes an incoming Ca
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The inaccuracy of memory states can
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C-engine Rule of Cachet Deriving Im
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Composite Mandatory Processor Rules
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memory regions simultaneously. In a
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Chapter 8 Conclusions This thesis h
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and heuristic policies. Mandatory r
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technique can be used to allow a ca
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Voluntary C-engine Rules Cstate Act
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FIFO Message Passing msg1 msg2 msg2
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[13] J. K. Archibald. The Cache Coh
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[41] A. Erlichson, N. Nuckolls, G.
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[71] J. Kuskin, D. Ofelt, M. Heinri
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[101] F. Pong and M. Dubois. A New
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