Design and Verification of Adaptive Cache Coherence Protocols ...

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Mandatory Processor Rules Instruction Cstate Action Next Cstate Loadl(a) Cell(a,v,Cleanb) retire Cell(a,v,Cleanb) P1 SF Cell(a,v,Dirtyb) retire Cell(a,v,Dirtyb) P2 SF Cell(a,v,Cleanw) retire Cell(a,v,Cleanw) P3 SF Cell(a,v,Dirtyw) retire Cell(a,v,Dirtyw) P4 SF Cell(a,v,Cleanm) retire Cell(a,v,Cleanm) P5 SF Cell(a,v,Dirtym) retire Cell(a,v,Dirtym) P6 SF Cell(a,v,WbPending) stall Cell(a,v,WbPending) P7 Cell(a,-,CachePending) stall Cell(a,-,CachePending) P8 a =2 cache stall, hCacheReq,ai !H Cell(a,-,CachePending) P9 SF Storel(a,v) Cell(a,-,Cleanb) retire Cell(a,v,Dirtyb) P10 SF Cell(a,-,Dirtyb) retire Cell(a,v,Dirtyb) P11 SF Cell(a,-,Cleanw) retire Cell(a,v,Dirtyw) P12 SF Cell(a,-,Dirtyw) retire Cell(a,v,Dirtyw) P13 SF Cell(a,-,Cleanm) retire Cell(a,v,Dirtym) P14 SF Cell(a,-,Dirtym) retire Cell(a,v,Dirtym) P15 SF Cell(a,v1,WbPending) stall Cell(a,v1,WbPending) P16 Cell(a,-,CachePending) stall Cell(a,-,CachePending) P17 a =2 cache stall, hCacheReq,ai !H Cell(a,-,CachePending) P18 SF Commit(a) Cell(a,v,Cleanb) retire Cell(a,v,Cleanb) P19 SF Cell(a,v,Dirtyb) stall, hWbb,a,vi!H Cell(a,v,WbPending) P20 SF Cell(a,v,Cleanw) retire Cell(a,v,Cleanw) P21 SF Cell(a,v,Dirtyw) stall, hDownwb,ai!H Cell(a,v,WbPending) P22 SF hWbb,a,vi!H Cell(a,v,Cleanm) retire Cell(a,v,Cleanm) P23 SF Cell(a,v,Dirtym) retire Cell(a,v,Dirtym) P24 SF Cell(a,v,WbPending) stall Cell(a,v,WbPending) P25 Cell(a,-,CachePending) stall Cell(a,-,CachePending) P26 a =2 cache retire a =2 cache P27 SF Reconcile(a) Cell(a,-,Cleanb) retire a =2 cache P28 SF Cell(a,v,Dirtyb) retire Cell(a,v,Dirtyb) P29 SF Cell(a,v,Cleanw) retire Cell(a,v,Cleanw) P30 SF Cell(a,v,Dirtyw) retire Cell(a,v,Dirtyw) P31 SF Cell(a,v,Cleanm) retire Cell(a,v,Cleanm) P32 SF Cell(a,v,Dirtym) retire Cell(a,v,Dirtym) P33 SF Cell(a,v,WbPending) stall Cell(a,v,WbPending) P34 Cell(a,-,CachePending) stall Cell(a,-,CachePending) P35 a =2 cache retire a =2 cache P36 SF Figure 7.11: Processor Rules of Cachet rules include the imperative cache engine rules, and additional rules to deal with downgrade requests from the memory. A cache processes a downgrade request as follows: When a cache receives a WP-to-Base downgrade request, if the address is cached under WP, the cache downgrades the cell to Base, and sends a Downwb message to the memory (Rules MC18 and MC19). However, if the address is cached under Base, or cached in the WbPending or CachePending state, or uncached, the cache simply discards the request (Rules MC16, MC17, MC20, MC21 and MC22). This is because the cache has already downgraded the cell before the downgrade request is received. When a cache receives a Migratory-to-WP downgrade request, if the address is cached under Migratory, the cache downgrades the cell to WP, and sends a Downmw or DownVmw message to the memory (Rules MC27 and MC28). However, if the address is cached under Base or WP, or cached in the WbPending or CachePending state, or uncached, the cache simply discards the request (Rules MC23, MC24, MC25, MC26, MC29, MC30 and MC31). 148
Voluntary C-engine Rules Cstate Action Next Cstate Cell(a,-,Cleanb) a =2 cache VC1 Cell(a,v,Dirtyb) hWbb,a,vi!H Cell(a,v,WbPending) VC2 Cell(a,v,Cleanw) hDownwb,ai!H Cell(a,v,Cleanb) VC3 Cell(a,v,Dirtyw) hDownwb,ai!H Cell(a,v,Dirtyb) VC4 Cell(a,v,Cleanm) hDownmw,ai!H Cell(a,v,Cleanw) VC5 Cell(a,v,Dirtym) hDownVmw,a,vi!H Cell(a,v,Cleanw) VC6 a =2 cache hCacheReq,ai !H Cell(a,-,CachePending) VC7 Mandatory C-engine Rules Msg from H Cstate Action Next Cstate hCacheb,a,vi Cell(a,-,CachePending) Cell(a,v,Cleanb) MC1 hCachew,a,vi Cell(a,-,Cleanb) Cell(a,v,Cleanw) MC2 Cell(a,v1,Dirtyb) Cell(a,v1,Dirtyw) MC3 Cell(a,v1,WbPending) Cell(a,v1,WbPending) MC4 Cell(a,-,CachePending) Cell(a,v,Cleanw) MC5 a =2 cache Cell(a,v,Cleanw) MC6 hUpwm,ai Cell(a,v,Cleanb) Cell(a,v,Cleanb) MC7 Cell(a,v,Dirtyb) Cell(a,v,Dirtyb) MC8 Cell(a,v,Cleanw) Cell(a,v,Cleanm) MC9 Cell(a,v,Dirtyw) Cell(a,v,Dirtym) MC10 Cell(a,v,WbPending) Cell(a,v,WbPending) MC11 Cell(a,-,CachePending) Cell(a,-,CachePending) MC12 a =2 cache a =2 cache MC13 hWbAckb,ai Cell(a,v,WbPending) Cell(a,v,Cleanb) MC14 hWbAckw,ai Cell(a,v,WbPending) Cell(a,v,Cleanw) MC15 hDownReqwb,ai Cell(a,v,Cleanb) Cell(a,v,Cleanb) MC16 Cell(a,v,Dirtyb) Cell(a,v,Dirtyb) MC17 Cell(a,v,Cleanw) hDownwb,ai!H Cell(a,v,Cleanb) MC18 Cell(a,v,Dirtyw) hDownwb,ai!H Cell(a,v,Dirtyb) MC19 Cell(a,v,WbPending) Cell(a,v,WbPending) MC20 Cell(a,-,CachePending) Cell(a,-,CachePending) MC21 a =2 cache a =2 cache MC22 hDownReqmw,ai Cell(a,v,Cleanb) Cell(a,v,Cleanb) MC23 Cell(a,v,Dirtyb) Cell(a,v,Dirtyb) MC24 Cell(a,v,Cleanw) Cell(a,v,Cleanw) MC25 Cell(a,v,Dirtyw) Cell(a,v,Dirtyw) MC26 Cell(a,v,Cleanm) hDownmw,ai!H Cell(a,v,Cleanw) MC27 Cell(a,v,Dirtym) hDownVmw,a,vi!H Cell(a,v,Cleanw) MC28 Cell(a,v,WbPending) Cell(a,v,WbPending) MC29 Cell(a,-,CachePending) Cell(a,-,CachePending) MC30 a =2 cache a =2 cache MC31 Figure 7.12: Cache Engine Rules of Cachet This is because the cache has already downgraded the cell before the downgrade request is received. 7.4.3 Memory Engine Rules of Cachet Figure 7.13 de nes the memory engine rules of Cachet. The memory engine rules consist of voluntary rules and mandatory rules. An incoming message can be processed or stalled when it is received. When a message is processed, it is removed from the incoming queue when a message is stalled, it remains in the incoming queue for later processing. Note that only CacheReq messages can be stalled a stalled message cannot block following messages from being processed. 149
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CSAIL Computer Science and Artifici
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Design and Veri cation of Adaptive
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I am truly grateful to my parents f
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4 The Base Cache Coherence Protocol
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List of Figures 1.1 Impact of Archi
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Chapter 1 Introduction Shared memor
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transparent and exposed only for lo
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Example 1: Can both registers r1 an
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and release locks, which guard ever
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that are interconnected with an o -
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although various techniques have be
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y showing that each processor can a
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s1 if p (s1) ! s2 where s1 and s2 a
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Program counter (pc) +1 Instruction
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Branch target buffer (btb) Program
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instruction is waiting to be dispat
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Current State: Proc(ia, rf , rob, b
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Rule Name mem pmb mpb Next mem Next
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Specification Implementation t 1 B
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Intuitively, \2P " means that \P is
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(a) (b) PC 1005 PC 2000 Instruction
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ewritten to s2 according to rule R.
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It can be shown that the relaxed di
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Chapter 3 The Commit-Reconcile & Fe
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Producer Storel(a,v) Commit(a) Cons
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Commit/Reconcile Purge Loadl/Commit
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instructions, because of the lack o
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CRF-Relaxed-Commit Rule Site(sache,
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3.4 Universality of the CRF Model M
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Translation from CRF to PSO: The Fe
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proc proc proc pmb mpb pmb mpb pmb
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Chapter 4 The Base Cache Coherence
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can be classi ed into two non-overl
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arbitrarily in an outgoing queue (t
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4.3 The Imperative Rules of the Bas
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Imperative Processor Rules Instruct
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Figure 4.5 de nes the rules of the
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4.5.2 Mapping from Base to CRF We d
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Base Imperative Rule CRF Rule IP1 (
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Base Rule Base Imperative Rule P1 I
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eceives a CacheReq message, it will
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e completed if it has an in nite nu
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SYS Sys(MSITE, SITEs) System MSITE
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Commit/Reconcile C-Receive-WbAck Ru
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message can be resumed eventually.
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If the memory state shows that the
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5.3.3 FIFO Message Passing The live
Page 99 and 100: Figure 5.7 gives the M-engine rules
Page 101 and 102: Backward-Message-Cache-to-Mem-for-W
Page 103 and 104: 5.4.3 Simulation of WP in CRF Theor
Page 105 and 106: WP Imperative Rule CRF Rules IP1 (L
Page 107 and 108: WP Rule WP Imperative & Directive R
Page 109 and 110: (4) Msg(H,id ,Cache,a,-)" 2 Cin id(
Page 111 and 112: This completes the proof according
Page 113 and 114: emains as CachePending, there mustb
Page 115 and 116: M-engine Rules Msg from id Mstate A
Page 117 and 118: Chapter 6 The Migratory Cache Coher
Page 119 and 120: Commit/Reconcile Send Purge Loadl/C
Page 121 and 122: Mandatory Processor Rules Instructi
Page 123 and 124: while the memory sends a FlushReq m
Page 125 and 126: Lemma 38 D is strongly terminating
Page 127 and 128: Migratory Imperative Rule CRF Rules
Page 129 and 130: Cell(a,v,C[id ]) 2 Mem(s) _ Cell(a,
Page 131 and 132: According to Theorem-C and Lemma 45
Page 133 and 134: CacheReq message. In the latter cas
Page 135 and 136: Chapter 7 Cachet: A Seamless Integr
Page 137 and 138: 7.1.1 Putting Things Together It is
Page 139 and 140: Writeback Operations In Cachet, a w
Page 141 and 142: Composite Message Equivalent Sequen
Page 143 and 144: Imperative Processor Rules Instruct
Page 145 and 146: Invalid Commit/Reconcile Receive Ca
Page 147 and 148: Composite Imperative C-engine Rules
Page 149: 7.4 The Cachet Cache Coherence Prot
Page 153 and 154: The memory processes an incoming Ca
Page 155 and 156: The inaccuracy of memory states can
Page 157 and 158: C-engine Rule of Cachet Deriving Im
Page 159 and 160: Composite Mandatory Processor Rules
Page 161 and 162: memory regions simultaneously. In a
Page 163 and 164: Chapter 8 Conclusions This thesis h
Page 165 and 166: and heuristic policies. Mandatory r
Page 167 and 168: technique can be used to allow a ca
Page 169 and 170: Voluntary C-engine Rules Cstate Act
Page 171 and 172: FIFO Message Passing msg1 msg2 msg2
Page 173 and 174: [13] J. K. Archibald. The Cache Coh
Page 175 and 176: [41] A. Erlichson, N. Nuckolls, G.
Page 177 and 178: [71] J. Kuskin, D. Ofelt, M. Heinri
Page 179 and 180: [101] F. Pong and M. Dubois. A New
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