Design and Verification of Adaptive Cache Coherence Protocols ...

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Proof The proof is based on a case analysis on the imperative ruleusedin the rewriting of `s1 ! s2' in Migratory. Let a be the address and id the cache identi er. Imperative Processor Rules If Rule IP1 (Loadl-on-Clean) applies, then Cell(a,v,Clean) 2 Cache id(s1) ^ Cell(a,v,Clean) 2 Cache id(s2) ) Cell(a,v,C[ ]) 2 Mem(s1) ^ Cell(a,v,C[ ]) 2 Mem(s2) (Lemma 41 ) ) f(s1) ! f(s2) (CRF-Cache, CRF-Loadl & CRF-Purge ) If Rule IP2 (Loadl-on-Dirty) applies, then Cell(a,v,Dirty) 2 Cache id(s1) ^ Cell(a,v,Dirty) 2 Cache id(s2) ) Cell(a,v,C[ ]) 2 Mem(s1) ^ Cell(a,v,C[ ]) 2 Mem(s2) (Lemma 41 ) ) f(s1) ! f(s2) (CRF-Cache, CRF-Loadl & CRF-Purge ) If Rule IP3 (Storel-on-Clean) applies, then Cell(a,-,Clean) 2 Cache id(s1) ^ Cell(a,v,Dirty) 2 Cache id(s2) ) Cell(a,-,C[ ]) 2 Mem(s1) ^ Cell(a,v,C[ ]) 2 Mem(s2) (Lemma 41 ) ) f(s1) ! f(s2) (CRF-Cache, CRF-Storel, CRF-Writeback & CRF-Purge ) If Rule IP4 (Storel-on-Dirty) applies, then Cell(a,-,Dirty) 2 Cache id(s1) ^ Cell(a,v,Dirty) 2 Cache id(s2) ) Cell(a,-,C[ ]) 2 Mem(s1) ^ Cell(a,v,C[ ]) 2 Mem(s2) (Lemma 41 ) ) f(s1) ! f(s2) (CRF-Cache, CRF-Storel, CRF-Writeback & CRF-Purge ) If Rule IP5 (Commit-on-Clean), IP6 (Commit-on-Dirty) orIP7(Commit-on-Invalid) applies, then f(s1) ! f(s2) (CRF-Commit ) If Rule IP8 (Reconcile-on-Clean), IP9 (Reconcile-on-Dirty) or IP10 (Reconcile-on-Invalid) applies, then f(s1) ! f(s2) (CRF-Reconcile ) Imperative M-engine Rules If Rule IM1 (M-Send-Cache) applies, then Draining Rules f(s1) =f(s2) If Rule IC1 (C-Send-Purge), IC2 (C-Send-Flush), IC3 (C-Receive-Cache), IM1 (M-Receive-Purge), IM2 (M-Receive-Flush), Message-Cache-to-Mem or Message-Mem-to-Cache applies, then f(s1) =f(s2) (Since the rule or its backward version is a draining rule) Figure 6.6 summarizes the simulation proof. 2 124
Migratory Imperative Rule CRF Rules IP1 (Loadl-on-Clean) CRF-Cache + CRF-Loadl + CRF-Purge IP2 (Loadl-on-Dirty) CRF-Cache + CRF-Loadl + CRF-Purge IP3 (Storel-on-Clean) CRF-Cache + CRF-Storel + CRF-Writeback + CRF-Purge IP4 (Storel-on-Dirty) CRF-Cache + CRF-Storel + CRF-Writeback + CRF-Purge IP5 (Commit-on-Clean) CRF-Commit IP6 (Commit-on-Dirty) CRF-Commit IP7 (Commit-on-Invalid) CRF-Commit IP8 (Reconcile-on-Clean) CRF-Reconcile IP9 (Reconcile-on-Dirty) CRF-Reconcile IP10 (Reconcile-on-Invalid) CRF-Reconcile IC1 (C-Send-Purge) IC2 (C-Send-Flush) IC3 (C-Receive-Cache) IM1 (M-Send-Cache) IM2 (M-Receive-Purge) IM3 (M-Receive-Flush) Message-Mem-to-Cache Message-Cache-to-Mem 6.4.4 Soundness of Migratory Figure 6.6: Simulation of Migratory in CRF The Migratory protocol de ned in Figure 6.4 contains integrated rules that are derived from the imperative and directive rules of Migratory. The imperative rules are given in Section 6.2. There are four directive rules that can be used to generate or discard directive messages. C-Send-CacheReq Rule Site(id , cache, in, out, pmb, mpb, proc) ! Site(id , cache, in, out Msg(id ,H,CacheReq,a), pmb, mpb, proc) C-Receive-FlushReq Rule Site(id , cache, Msg(H,id ,FlushReq,a) in, out, pmb, mpb, proc) ! Site(id , cache, in, out, pmb, mpb, proc) M-Send-FlushReq Rule Msite(mem, in, out) ! Msite(mem, in, out Msg(H,id ,FlushReq,a)) M-Receive-CacheReq Rule Msite(mem, Msg(id ,H,CacheReq,a) in, out) ! Msite(mem, in, out) Figure 6.7 gives the imperative and directive rules used in the derivation for each Migratory rule. In the derivation, CachePending and T[id ] used in the integrated rules are mapped to Invalid and C[id ] of the imperative rules, respectively. Therefore, Migratory is a sound implementation of the CRF model. 125
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CSAIL Computer Science and Artifici
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Design and Veri cation of Adaptive
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I am truly grateful to my parents f
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4 The Base Cache Coherence Protocol
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List of Figures 1.1 Impact of Archi
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Chapter 1 Introduction Shared memor
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transparent and exposed only for lo
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Example 1: Can both registers r1 an
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and release locks, which guard ever
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that are interconnected with an o -
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although various techniques have be
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y showing that each processor can a
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s1 if p (s1) ! s2 where s1 and s2 a
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Program counter (pc) +1 Instruction
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Branch target buffer (btb) Program
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instruction is waiting to be dispat
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Current State: Proc(ia, rf , rob, b
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Rule Name mem pmb mpb Next mem Next
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Specification Implementation t 1 B
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Intuitively, \2P " means that \P is
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(a) (b) PC 1005 PC 2000 Instruction
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ewritten to s2 according to rule R.
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It can be shown that the relaxed di
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Chapter 3 The Commit-Reconcile & Fe
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Producer Storel(a,v) Commit(a) Cons
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Commit/Reconcile Purge Loadl/Commit
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instructions, because of the lack o
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CRF-Relaxed-Commit Rule Site(sache,
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3.4 Universality of the CRF Model M
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Translation from CRF to PSO: The Fe
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proc proc proc pmb mpb pmb mpb pmb
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Chapter 4 The Base Cache Coherence
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can be classi ed into two non-overl
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arbitrarily in an outgoing queue (t
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4.3 The Imperative Rules of the Bas
Page 75 and 76: Imperative Processor Rules Instruct
Page 77 and 78: Figure 4.5 de nes the rules of the
Page 79 and 80: 4.5.2 Mapping from Base to CRF We d
Page 81 and 82: Base Imperative Rule CRF Rule IP1 (
Page 83 and 84: Base Rule Base Imperative Rule P1 I
Page 85 and 86: eceives a CacheReq message, it will
Page 87 and 88: e completed if it has an in nite nu
Page 89 and 90: SYS Sys(MSITE, SITEs) System MSITE
Page 91 and 92: Commit/Reconcile C-Receive-WbAck Ru
Page 93 and 94: message can be resumed eventually.
Page 95 and 96: If the memory state shows that the
Page 97 and 98: 5.3.3 FIFO Message Passing The live
Page 99 and 100: Figure 5.7 gives the M-engine rules
Page 101 and 102: Backward-Message-Cache-to-Mem-for-W
Page 103 and 104: 5.4.3 Simulation of WP in CRF Theor
Page 105 and 106: WP Imperative Rule CRF Rules IP1 (L
Page 107 and 108: WP Rule WP Imperative & Directive R
Page 109 and 110: (4) Msg(H,id ,Cache,a,-)" 2 Cin id(
Page 111 and 112: This completes the proof according
Page 113 and 114: emains as CachePending, there mustb
Page 115 and 116: M-engine Rules Msg from id Mstate A
Page 117 and 118: Chapter 6 The Migratory Cache Coher
Page 119 and 120: Commit/Reconcile Send Purge Loadl/C
Page 121 and 122: Mandatory Processor Rules Instructi
Page 123 and 124: while the memory sends a FlushReq m
Page 125: Lemma 38 D is strongly terminating
Page 129 and 130: Cell(a,v,C[id ]) 2 Mem(s) _ Cell(a,
Page 131 and 132: According to Theorem-C and Lemma 45
Page 133 and 134: CacheReq message. In the latter cas
Page 135 and 136: Chapter 7 Cachet: A Seamless Integr
Page 137 and 138: 7.1.1 Putting Things Together It is
Page 139 and 140: Writeback Operations In Cachet, a w
Page 141 and 142: Composite Message Equivalent Sequen
Page 143 and 144: Imperative Processor Rules Instruct
Page 145 and 146: Invalid Commit/Reconcile Receive Ca
Page 147 and 148: Composite Imperative C-engine Rules
Page 149 and 150: 7.4 The Cachet Cache Coherence Prot
Page 151 and 152: Voluntary C-engine Rules Cstate Act
Page 153 and 154: The memory processes an incoming Ca
Page 155 and 156: The inaccuracy of memory states can
Page 157 and 158: C-engine Rule of Cachet Deriving Im
Page 159 and 160: Composite Mandatory Processor Rules
Page 161 and 162: memory regions simultaneously. In a
Page 163 and 164: Chapter 8 Conclusions This thesis h
Page 165 and 166: and heuristic policies. Mandatory r
Page 167 and 168: technique can be used to allow a ca
Page 169 and 170: Voluntary C-engine Rules Cstate Act
Page 171 and 172: FIFO Message Passing msg1 msg2 msg2
Page 173 and 174: [13] J. K. Archibald. The Cache Coh
Page 175 and 176: [41] A. Erlichson, N. Nuckolls, G.
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[71] J. Kuskin, D. Ofelt, M. Heinri
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[101] F. Pong and M. Dubois. A New
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