Notations Given a system term s, we use Mem(s), Min(s) <strong>and</strong> Mout(s) to represent the memory, the memory's incoming queue <strong>and</strong> the memory's outgoing queue, respectively. For a cache site id , we use <strong>Cache</strong>id (s), Cinid(s), Coutid(s), Pmbid(s), Mpbid(s) <strong>and</strong> Procid(s) to represent the cache, the incoming queue, the outgoing queue, the processor-to-memory bu er, the memory-to-processor bu er <strong>and</strong> the processor, respectively. More precisely, let s be the term Sys(Msite(mem, min, mout), Site(id , cache, cin, cout, pmb, mpb, proc) j sites) We de ne the following notations: Mem(s) mem Min(s) min Mout(s) mout <strong>Cache</strong> id(s) cache Cin id(s) cin Cout id(s) cout Pmb id(s) pmb Mpb id (s) mpb Proc id(s) proc We say a message is in transit from a cache to the memory if the message is in the cache's outgoing queue or the memory's incoming queue. We say a message is in transit from the memory to a cache if the message is in the memory's outgoing queue or the cache's incoming queue. We use shorth<strong>and</strong> notation MoutCinid(s) to represent the messages in transit from the memory to cache site id , <strong>and</strong> MinCoutid(s) the messages in transit from cache site id to the memory. That is: msg 2 MoutCin id(s) i msg 2 Mout(s) _ msg 2 Cin id (s) msg 2 MinCout id(s) i msg 2 Min(s) _ msg 2 Cout id(s) Let msg1 <strong>and</strong> msg2 be messages between the same source <strong>and</strong> destination regarding the same address. We say messagemsg1 precedes message msg2 (or msg2 follows msg1), if the following condition is satis ed: msg1 <strong>and</strong> msg2 arebothinthesource's outgoing queue, <strong>and</strong> msg1 is in front <strong>of</strong>message msg2 or msg1 <strong>and</strong> msg2 are both in the destination's incoming queue, <strong>and</strong> msg1 is in front <strong>of</strong> message msg2 or msg1 is in the destination's incoming queue <strong>and</strong> msg2 is in the source's outgoing queue. We use notation msg" to represent that message msg has no preceding message, <strong>and</strong> notation msg# to represent that message msg has no following message. Notation msg l means that message msg has no preceding or following message (that is, it is the only message regarding the address between the source <strong>and</strong> destination). 70
4.3 The Imperative Rules <strong>of</strong> the Base Protocol The Base protocol is a simple implementation <strong>of</strong> the CRF model. It is a directory-less protocol in the sense that the memory maintains no directory information about where an address is cached. In Base, the memory behaves as the rendezvous: when a processor executes a Commit on a dirty cell, it writes the data back tothe memory before completing the Commit when a processor executes a Reconcile on a clean cell, it purges the data before completing the Reconcile (thus a following Loadl to the same address must retrieve data from the memory). The Base protocol employs two stable cache states, Clean <strong>and</strong> Dirty, <strong>and</strong> two transient cache states, <strong>Cache</strong>Pending <strong>and</strong> WbPending. When an address is not resident in a cache, we say the cache state is Invalid or the address is cached in the Invalid state. There are four messages, <strong>Cache</strong>Req, <strong>Cache</strong>, Wb <strong>and</strong> WbAck. The imperative rules <strong>of</strong> Base specify how instructions can be executed on cache cells in appropriate states <strong>and</strong> how data can be propagated between the memory <strong>and</strong> caches. They are responsible for ensuring the soundness <strong>of</strong> the protocol, that is, the system only exhibits behaviors that are permitted by the CRF model. The imperative ruleshave three sets <strong>of</strong> rules, the processor rules, the cache engine rules <strong>and</strong> the memory engine rules. Processor Rules: A Loadl or Storel instruction can be performed if the address is cached in the Clean or Dirty state. A Commit instruction can be performed if the address is uncached or cached in the Clean state. A Reconcile instruction can be performed if the address is uncached or cached in the Dirty state. Loadl-on-Clean Rule Site(id , Cell(a,v,Clean) j cache, in, out, ht,Loadl(a)ipmb, mpb, proc) ! Site(id , Cell(a,v,Clean) j cache, in, out, pmb, mpbjht,vi, proc) Loadl-on-Dirty Rule Site(id , Cell(a,v,Dirty) j cache, in, out, ht,Loadl(a)ipmb, mpb, proc) ! Site(id , Cell(a,v,Dirty) j cache, in, out, pmb, mpbjht,vi, proc) Storel-on-Clean Rule Site(id , Cell(a,-,Clean) j cache, in, out, ht,Storel(a,v)ipmb, mpb, proc) ! Site(id , Cell(a,v,Dirty) j cache, in, out, pmb, mpbjht,Acki, proc) Storel-on-Dirty Rule Site(id , Cell(a,-,Dirty) j cache, in, out, ht,Storel(a,v)ipmb, mpb, proc) ! Site(id , Cell(a,v,Dirty) j cache, in, out, pmb, mpbjht,Acki, proc) Commit-on-Clean Rule Site(id , Cell(a,v,Clean) j cache, in, out, ht,Commit(a)ipmb, mpb, proc) ! Site(id , Cell(a,v,Clean) j cache, in, out, pmb, mpbjht,Acki, proc) Commit-on-Invalid Rule Site(id , cache, in, out, ht,Commit(a)ipmb, mpb, proc) if a =2 cache ! Site(id , cache, in, out, pmb, mpbjht,Acki, proc) 71
- Page 1:
CSAIL Computer Science and Artifici
- Page 5:
Design and Veri cation of Adaptive
- Page 8 and 9:
I am truly grateful to my parents f
- Page 10 and 11:
4 The Base Cache Coherence Protocol
- Page 13 and 14:
List of Figures 1.1 Impact of Archi
- Page 15 and 16:
Chapter 1 Introduction Shared memor
- Page 17 and 18:
transparent and exposed only for lo
- Page 19 and 20:
Example 1: Can both registers r1 an
- Page 21 and 22: and release locks, which guard ever
- Page 23 and 24: that are interconnected with an o -
- Page 25 and 26: although various techniques have be
- Page 27 and 28: y showing that each processor can a
- Page 29 and 30: s1 if p (s1) ! s2 where s1 and s2 a
- Page 31 and 32: Program counter (pc) +1 Instruction
- Page 33 and 34: Branch target buffer (btb) Program
- Page 35 and 36: instruction is waiting to be dispat
- Page 37 and 38: Current State: Proc(ia, rf , rob, b
- Page 39 and 40: Rule Name mem pmb mpb Next mem Next
- Page 41 and 42: Specification Implementation t 1 B
- Page 43 and 44: Intuitively, \2P " means that \P is
- Page 45 and 46: (a) (b) PC 1005 PC 2000 Instruction
- Page 47 and 48: ewritten to s2 according to rule R.
- Page 49 and 50: It can be shown that the relaxed di
- Page 51 and 52: Chapter 3 The Commit-Reconcile & Fe
- Page 53 and 54: Producer Storel(a,v) Commit(a) Cons
- Page 55 and 56: Commit/Reconcile Purge Loadl/Commit
- Page 57 and 58: instructions, because of the lack o
- Page 59 and 60: CRF-Relaxed-Commit Rule Site(sache,
- Page 61 and 62: 3.4 Universality of the CRF Model M
- Page 63 and 64: Translation from CRF to PSO: The Fe
- Page 65 and 66: proc proc proc pmb mpb pmb mpb pmb
- Page 67 and 68: Chapter 4 The Base Cache Coherence
- Page 69 and 70: can be classi ed into two non-overl
- Page 71: arbitrarily in an outgoing queue (t
- Page 75 and 76: Imperative Processor Rules Instruct
- Page 77 and 78: Figure 4.5 de nes the rules of the
- Page 79 and 80: 4.5.2 Mapping from Base to CRF We d
- Page 81 and 82: Base Imperative Rule CRF Rule IP1 (
- Page 83 and 84: Base Rule Base Imperative Rule P1 I
- Page 85 and 86: eceives a CacheReq message, it will
- Page 87 and 88: e completed if it has an in nite nu
- Page 89 and 90: SYS Sys(MSITE, SITEs) System MSITE
- Page 91 and 92: Commit/Reconcile C-Receive-WbAck Ru
- Page 93 and 94: message can be resumed eventually.
- Page 95 and 96: If the memory state shows that the
- Page 97 and 98: 5.3.3 FIFO Message Passing The live
- Page 99 and 100: Figure 5.7 gives the M-engine rules
- Page 101 and 102: Backward-Message-Cache-to-Mem-for-W
- Page 103 and 104: 5.4.3 Simulation of WP in CRF Theor
- Page 105 and 106: WP Imperative Rule CRF Rules IP1 (L
- Page 107 and 108: WP Rule WP Imperative & Directive R
- Page 109 and 110: (4) Msg(H,id ,Cache,a,-)" 2 Cin id(
- Page 111 and 112: This completes the proof according
- Page 113 and 114: emains as CachePending, there mustb
- Page 115 and 116: M-engine Rules Msg from id Mstate A
- Page 117 and 118: Chapter 6 The Migratory Cache Coher
- Page 119 and 120: Commit/Reconcile Send Purge Loadl/C
- Page 121 and 122: Mandatory Processor Rules Instructi
- Page 123 and 124:
while the memory sends a FlushReq m
- Page 125 and 126:
Lemma 38 D is strongly terminating
- Page 127 and 128:
Migratory Imperative Rule CRF Rules
- Page 129 and 130:
Cell(a,v,C[id ]) 2 Mem(s) _ Cell(a,
- Page 131 and 132:
According to Theorem-C and Lemma 45
- Page 133 and 134:
CacheReq message. In the latter cas
- Page 135 and 136:
Chapter 7 Cachet: A Seamless Integr
- Page 137 and 138:
7.1.1 Putting Things Together It is
- Page 139 and 140:
Writeback Operations In Cachet, a w
- Page 141 and 142:
Composite Message Equivalent Sequen
- Page 143 and 144:
Imperative Processor Rules Instruct
- Page 145 and 146:
Invalid Commit/Reconcile Receive Ca
- Page 147 and 148:
Composite Imperative C-engine Rules
- Page 149 and 150:
7.4 The Cachet Cache Coherence Prot
- Page 151 and 152:
Voluntary C-engine Rules Cstate Act
- Page 153 and 154:
The memory processes an incoming Ca
- Page 155 and 156:
The inaccuracy of memory states can
- Page 157 and 158:
C-engine Rule of Cachet Deriving Im
- Page 159 and 160:
Composite Mandatory Processor Rules
- Page 161 and 162:
memory regions simultaneously. In a
- Page 163 and 164:
Chapter 8 Conclusions This thesis h
- Page 165 and 166:
and heuristic policies. Mandatory r
- Page 167 and 168:
technique can be used to allow a ca
- Page 169 and 170:
Voluntary C-engine Rules Cstate Act
- Page 171 and 172:
FIFO Message Passing msg1 msg2 msg2
- Page 173 and 174:
[13] J. K. Archibald. The Cache Coh
- Page 175 and 176:
[41] A. Erlichson, N. Nuckolls, G.
- Page 177 and 178:
[71] J. Kuskin, D. Ofelt, M. Heinri
- Page 179 and 180:
[101] F. Pong and M. Dubois. A New