Design and Verification of Adaptive Cache Coherence Protocols ...

message can be resumed eventually. To ensure liveness, the memory must send a purge request
to the caches in which the address is cached to force the address to be purged.
We introduce two directive messages, CacheReq and PurgeReq, for this purpose. A cache
can send a CacheReq message to the memory to request for a data copy the memory can
send a PurgeReq message to a cache to force a clean copy to be purged or a dirty copy to be
written back. In addition, we maintain some information about outstanding directive messages
by splitting certain imperative cache and memory states. The Invalid state in the imperative
rules corresponds to Invalid and CachePending in the integrated protocol, where CachePending
implies that a CacheReq message has been sent to the memory. The T[dir, ] state in the
imperative rules corresponds to T[dir, ] and C[dir] in the integrated protocol, where T[dir, ]
implies that a PurgeReq message has been multicast to cache sites dir.
Figure 5.5 de nes the rules of the WP protocol. The tabular description can be easily
translated into formal TRS rules (cases that are not speci ed represent illegal or unreachable
states). The processor rules are all mandatory rules. The cache engine and memory engine
rules are categorized into mandatory and voluntary rules. Each mandatory rule is weakly fair
in that if it can be applied, it must be applied eventually or become impossible to apply at some
time. A mandatory rule marked with `SF' means the rule requires strong fairness to ensure
the liveness of the system. The notation `msg ! dir' means sending the message msg to the
destinations represented by directory dir.
A processor rule may retire or stall an instruction depending on the cache state of the
address. When an instruction is retired, it is removed from the processor-to-memory bu er
and the corresponding value or reply is sent to the memory-to-processor bu er. When an
instruction is stalled, it remains in the processor-to-memory bu er for later processing. A
stalled instruction does not necessarily block other instructions to be executed.
An incoming message can be processed or stalled depending on the memory state of the
address. When a message is processed, it is removed from the incoming queue. When a message
is stalled, it remains in the incoming queue for later processing (only CacheReq messages can
be stalled). A stalled message is bu ered properly to avoid blocking following messages.
5.3.1 Mandatory Rules
The processor rules are similar to those in the Base protocol, except that a Reconcile instruction
can complete even when the address is cached in the Clean state. On acache miss, the cache
sends a cache request to the memory and sets the cache state to be CachePending until the
requested data is received. On a Commit instruction, if the address is cached in the Dirty
state, the cache writes the data back to the memory and sets the cache state to be WbPending
until a writeback acknowledgment is received. An instruction remains stalled when it cannot
be completed in the current cache state.
When the memory receives a CacheReq message, it processes the message according to the
memory state. If the address is already cached in the cache, the cache request is discarded.
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