Design and Verification of Adaptive Cache Coherence Protocols ...

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Proof We rst show some properties that are needed for the proof. All these properties can be veri ed by simply checking the Migratory rules. A cache sends a CacheReq message to the memory whenever it changes the state of a cache cell to CachePending. Cell(a,-,CachePending) =2 Cache id( ) ^ Cell(a,-,CachePending) 2 Cache id( ) ) Msg(id ,H,CacheReq,a)# 2 Cout id( ) The CachePending state can only be changed to the Clean state. Cell(a,-,CachePending) 2 Cache id( ) ^ Cell(a,-,CachePending) =2 Cache id( ) ) Cell(a,-,Clean) 2 Cache id( ) Acache cannot send any message to the memory while the cache state is CachePending. Cell(a,-,CachePending) 2 Cache id( ) ^ msg# 2 MinCout id( ) ) msg# 2 MinCout id( ) We then prove the lemma under the assumption that the cache's outgoing queue contains a CacheReq message and the CacheReq message has no following message. According to Theorem-C and Lemma 45, Cell(a,-,CachePending) 2 Cache id( ) ^ Msg(id ,H,CacheReq,a)# 2 Cout id( ) (Cell(a,-,CachePending) 2 Cache id( ) ^ Msg(id ,H,CacheReq,a)# 2 Min( )) _ Cell(a,-,Clean) 2 Cache id( ) According to Theorem-C and Lemma 48, Cell(a,-,CachePending) 2 Cache id( ) ^ Msg(id ,H,CacheReq,a)# 2 Min( ) (Cell(a,-,CachePending) 2 Cache id( ) ^ Msg(id ,H,CacheReq,a) l 2 Min( )) _ Cell(a,-,Clean) 2 Cache id( ) According to Lemmas 44, 45, and 48, Cell(a,-,CachePending) 2 Cache id( ) ^ Msg(id ,H,CacheReq,a) l 2 Min( ) Msg(H,id ,Cache,a,-) 2 MoutCin id( ) Msg(H,id ,Cache,a,-) 2 Cin id( ) Msg(H,id ,Cache,a,-)" 2 Cin id( ) Cell(a,-,Clean) 2 Cache id( ) Thus, Cell(a,-,CachePending) 2 Cache id( ) ^ Msg(id ,H,CacheReq,a)# 2 Cout id ( ) Cell(a,-,Clean) 2 Cache id( ) This completes the proof according to Theorem-A. 2 The proof above can be described in a more intuitive way. A cache generates a CacheReq message each timeitchanges the cache state of an address to CachePending. When the memory receives a CacheReq message from cache id , if the memory state is C[ ], the memory sends a Cache message to cache id if the memory state is C[id ] or T[id ], the memory ignores the 130
CacheReq message. In the latter case, if the cache state remains as CachePending, there is a Cache message in transit from the memory to cache id according to Lemma 44 (note that the CacheReq message has no following message since the cache cannot issue any message while the cache state is CachePending, and FIFO message passing guarantees that any preceding message has been received before the CacheReq message is received). When the cache receives the Cache message, it caches the data and sets the cache state to Clean. It is worth pointing out that although the CacheReq message can be stalled at the memory, the stalled message will be processed eventually. 6.5.2 Liveness of Migratory Lemma 50 ensures that whenever a processor intends to execute an instruction, the cache cell will be set to an appropriate state eventually. For a Loadl or Storel, the cache state will be set to Clean or Dirty for a Commit or Reconcile, the cache state will be set to Clean, Dirty or Invalid. Lemma 50 Given a Migratory sequence , (1) Loadl(a) 2 Pmb id( ) Loadl(a) 2 Pmb id( ) ^ (Cell(a,-,Clean) 2 Cache id( ) _ Cell(a,-,Dirty) 2 Cache id( )) (2) Storel(a,-) 2 Pmb id( ) Storel(a,-) 2 Pmb id( ) ^ (Cell(a,-,Clean) 2 Cache id( ) _ Cell(a,-,Dirty) 2 Cache id( )) (3) Commit(a) 2 Pmb id( ) Commit(a) 2 Pmb id ( ) ^ (Cell(a,-,Clean) 2 Cache id( ) _ Cell(a,-,Dirty) 2 Cache id( ) _ a =2 Cache id( )) (4) Reconcile(a) 2 Pmb id( ) Reconcile(a) 2 Pmb id( ) ^ (Cell(a,-,Clean) 2 Cache id( ) _ Cell(a,-,Dirty) 2 Cache id( ) _ a =2 Cache id( )) Proof We rst show that whenever a processor intends to execute an instruction, the cache cell will be set to an appropriate state so that the instruction can be completed. This can be represented by the following proposition the proof follows from Lemmas 45 and 49. Loadl(a) 2 Pmb id( ) Cell(a,-,Clean) 2 Cache id( ) _ Cell(a,-,Dirty) 2 Cache id( ) Storel(a,-) 2 Pmb id( ) Cell(a,-,Clean) 2 Cache id( ) _ Cell(a,-,Dirty) 2 Cache id( ) Commit(a) 2 Pmb id ( ) Cell(a,-,Clean) 2 Cache id( ) _ Cell(a,-,Dirty) 2 Cache id( ) _ a =2 Cache id( ) Reconcile(a) 2 Pmb id( ) Cell(a,-,Clean) 2 Cache id( ) _ Cell(a,-,Dirty) 2 Cache id( ) _ a =2 Cache id( ) We then show that an instruction can be completed only when the address is cached in an appropriate state. This can be represented by the following proposition, which can be veri ed by simplychecking the Migratory rules that allow an instruction to be retired. 131
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CSAIL Computer Science and Artifici
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Design and Veri cation of Adaptive
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I am truly grateful to my parents f
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4 The Base Cache Coherence Protocol
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List of Figures 1.1 Impact of Archi
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Chapter 1 Introduction Shared memor
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transparent and exposed only for lo
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Example 1: Can both registers r1 an
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and release locks, which guard ever
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that are interconnected with an o -
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although various techniques have be
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y showing that each processor can a
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s1 if p (s1) ! s2 where s1 and s2 a
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Program counter (pc) +1 Instruction
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Branch target buffer (btb) Program
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instruction is waiting to be dispat
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Current State: Proc(ia, rf , rob, b
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Rule Name mem pmb mpb Next mem Next
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Specification Implementation t 1 B
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Intuitively, \2P " means that \P is
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(a) (b) PC 1005 PC 2000 Instruction
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ewritten to s2 according to rule R.
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It can be shown that the relaxed di
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Chapter 3 The Commit-Reconcile & Fe
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Producer Storel(a,v) Commit(a) Cons
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Commit/Reconcile Purge Loadl/Commit
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instructions, because of the lack o
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CRF-Relaxed-Commit Rule Site(sache,
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3.4 Universality of the CRF Model M
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Translation from CRF to PSO: The Fe
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proc proc proc pmb mpb pmb mpb pmb
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Chapter 4 The Base Cache Coherence
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can be classi ed into two non-overl
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arbitrarily in an outgoing queue (t
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4.3 The Imperative Rules of the Bas
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Imperative Processor Rules Instruct
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Figure 4.5 de nes the rules of the
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4.5.2 Mapping from Base to CRF We d
Page 81 and 82: Base Imperative Rule CRF Rule IP1 (
Page 83 and 84: Base Rule Base Imperative Rule P1 I
Page 85 and 86: eceives a CacheReq message, it will
Page 87 and 88: e completed if it has an in nite nu
Page 89 and 90: SYS Sys(MSITE, SITEs) System MSITE
Page 91 and 92: Commit/Reconcile C-Receive-WbAck Ru
Page 93 and 94: message can be resumed eventually.
Page 95 and 96: If the memory state shows that the
Page 97 and 98: 5.3.3 FIFO Message Passing The live
Page 99 and 100: Figure 5.7 gives the M-engine rules
Page 101 and 102: Backward-Message-Cache-to-Mem-for-W
Page 103 and 104: 5.4.3 Simulation of WP in CRF Theor
Page 105 and 106: WP Imperative Rule CRF Rules IP1 (L
Page 107 and 108: WP Rule WP Imperative & Directive R
Page 109 and 110: (4) Msg(H,id ,Cache,a,-)" 2 Cin id(
Page 111 and 112: This completes the proof according
Page 113 and 114: emains as CachePending, there mustb
Page 115 and 116: M-engine Rules Msg from id Mstate A
Page 117 and 118: Chapter 6 The Migratory Cache Coher
Page 119 and 120: Commit/Reconcile Send Purge Loadl/C
Page 121 and 122: Mandatory Processor Rules Instructi
Page 123 and 124: while the memory sends a FlushReq m
Page 125 and 126: Lemma 38 D is strongly terminating
Page 127 and 128: Migratory Imperative Rule CRF Rules
Page 129 and 130: Cell(a,v,C[id ]) 2 Mem(s) _ Cell(a,
Page 131: According to Theorem-C and Lemma 45
Page 135 and 136: Chapter 7 Cachet: A Seamless Integr
Page 137 and 138: 7.1.1 Putting Things Together It is
Page 139 and 140: Writeback Operations In Cachet, a w
Page 141 and 142: Composite Message Equivalent Sequen
Page 143 and 144: Imperative Processor Rules Instruct
Page 145 and 146: Invalid Commit/Reconcile Receive Ca
Page 147 and 148: Composite Imperative C-engine Rules
Page 149 and 150: 7.4 The Cachet Cache Coherence Prot
Page 151 and 152: Voluntary C-engine Rules Cstate Act
Page 153 and 154: The memory processes an incoming Ca
Page 155 and 156: The inaccuracy of memory states can
Page 157 and 158: C-engine Rule of Cachet Deriving Im
Page 159 and 160: Composite Mandatory Processor Rules
Page 161 and 162: memory regions simultaneously. In a
Page 163 and 164: Chapter 8 Conclusions This thesis h
Page 165 and 166: and heuristic policies. Mandatory r
Page 167 and 168: technique can be used to allow a ca
Page 169 and 170: Voluntary C-engine Rules Cstate Act
Page 171 and 172: FIFO Message Passing msg1 msg2 msg2
Page 173 and 174: [13] J. K. Archibald. The Cache Coh
Page 175 and 176: [41] A. Erlichson, N. Nuckolls, G.
Page 177 and 178: [71] J. Kuskin, D. Ofelt, M. Heinri
Page 179 and 180: [101] F. Pong and M. Dubois. A New
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