Design and Verification of Adaptive Cache Coherence Protocols ...

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Processor Rule of Cachet Deriving Imperative & Directive Rules P1 IP1 P2 IP2 P3 IP3 P4 IP4 P5 IP5 P6 IP6 P7 P8 P9 IC7 P10 IP7 P11 IP8 P12 IP9 P13 IP10 P14 IP11 P15 IP12 P16 P17 P18 IC7 P19 IP13 P20 IC2 P21 IP14 P22 IC4 + IC2 P23 IP15 P24 IP16 P25 P26 P27 IP17 P28 IC1+IP23 P29 IP18 P30 IP19 P31 IP20 P32 IP21 P33 IP22 P34 P35 P36 IP23 Figure 7.14: Derivation of Processor Rules of Cachet Figures 7.14, 7.15 and 7.16 give the derivations of the processor rules, the cache engine rules and the memory engine rules, respectively. In the derivation, the Cw[dir] state used in the integrated rules corresponds to the Tw[dir, ] state of the imperative rules the Cm[id ] and T 0 m [id ] states used in the integrated rules correspond to the Tm[id , ] state of the imperative rules. 7.5 The Composite Rules of Cachet In this section, we will present some composite rules that involve the composite messages. Since a composite message behaves as a sequence of basic messages, a composite rule can always be simulated by some basic rules. Figure 7.17 de nes the composite rules of Cachet. When a Commit instruction is performed on an address that is cached in the Dirty state of WP, the cache can write the data back to the memory via a Wbw message. The instruction remains stalled until the writeback operation is acknowledged. 154
C-engine Rule of Cachet Deriving Imperative & Directive Rules VC1 IC1 VC2 IC2 VC3 IC3 VC4 IC4 VC5 IC5 VC6 IC6 VC7 IC7 MC1 IC8 MC2 IC1 + IC13 MC3 IC10 MC4 IC11 MC5 IC12 MC6 IC13 MC7 IC14 MC8 IC15 MC9 IC16 MC10 IC17 MC11 IC18 MC12 IC19 MC13 IC20 MC14 IC21 MC15 IC22 MC16 Receive-DownReqwb MC17 Receive-DownReqwb MC18 Receive-DownReqwb +IC3 MC19 Receive-DownReqwb +IC4 MC20 Receive-DownReqwb MC21 Receive-DownReqwb MC22 Receive-DownReqwb MC23 Receive-DownReqmw MC24 Receive-DownReqmw MC25 Receive-DownReqmw MC26 Receive-DownReqmw MC27 Receive-DownReqmw + IC5 MC28 Receive-DownReqmw + IC6 MC29 Receive-DownReqmw MC30 Receive-DownReqmw MC31 Receive-DownReqmw Figure 7.15: Derivation of Cache Engine Rules of Cachet The composite C-engine rules include the composite imperative C-engine rules given in Figure 7.9, and some additional rules that are needed to process Migratory-to-Base downgrade requests. A Migratory-to-Base message behaves as a DownReqmw followed by aDownReqwb. The memory may send a composite message to a cache under certain circumstances. If the memory state is Cw[ ], the memory can send a Migratory message to supply a Migratory copy to a cache site. If the memory state is Cm[id ], the memory can send a DownReqmb message to cache site id to downgrade the cache cell from Migratory to Base. In addition, the memory can acknowledge the last resumed writeback operation with a WbAckm message to allow the cache to retain a Migratory copy. When the memory receives a composite message, it processes the message as a sequence of basic messages. The memory treats a Wbw message as a Downwb followed by aWbb, a Downmb message as aDownmw followed by aDownwb, andaDownVmb message as a DownVmw followed by aDownwb. 155
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CSAIL Computer Science and Artifici
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Design and Veri cation of Adaptive
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I am truly grateful to my parents f
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4 The Base Cache Coherence Protocol
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List of Figures 1.1 Impact of Archi
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Chapter 1 Introduction Shared memor
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transparent and exposed only for lo
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Example 1: Can both registers r1 an
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and release locks, which guard ever
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that are interconnected with an o -
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although various techniques have be
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y showing that each processor can a
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s1 if p (s1) ! s2 where s1 and s2 a
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Program counter (pc) +1 Instruction
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Branch target buffer (btb) Program
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instruction is waiting to be dispat
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Current State: Proc(ia, rf , rob, b
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Rule Name mem pmb mpb Next mem Next
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Specification Implementation t 1 B
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Intuitively, \2P " means that \P is
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(a) (b) PC 1005 PC 2000 Instruction
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ewritten to s2 according to rule R.
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It can be shown that the relaxed di
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Chapter 3 The Commit-Reconcile & Fe
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Producer Storel(a,v) Commit(a) Cons
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Commit/Reconcile Purge Loadl/Commit
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instructions, because of the lack o
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CRF-Relaxed-Commit Rule Site(sache,
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3.4 Universality of the CRF Model M
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Translation from CRF to PSO: The Fe
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proc proc proc pmb mpb pmb mpb pmb
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Chapter 4 The Base Cache Coherence
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can be classi ed into two non-overl
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arbitrarily in an outgoing queue (t
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4.3 The Imperative Rules of the Bas
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Imperative Processor Rules Instruct
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Figure 4.5 de nes the rules of the
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4.5.2 Mapping from Base to CRF We d
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Base Imperative Rule CRF Rule IP1 (
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Base Rule Base Imperative Rule P1 I
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eceives a CacheReq message, it will
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e completed if it has an in nite nu
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SYS Sys(MSITE, SITEs) System MSITE
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Commit/Reconcile C-Receive-WbAck Ru
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message can be resumed eventually.
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If the memory state shows that the
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5.3.3 FIFO Message Passing The live
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Figure 5.7 gives the M-engine rules
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Backward-Message-Cache-to-Mem-for-W
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5.4.3 Simulation of WP in CRF Theor
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Page 107 and 108: WP Rule WP Imperative & Directive R
Page 109 and 110: (4) Msg(H,id ,Cache,a,-)" 2 Cin id(
Page 111 and 112: This completes the proof according
Page 113 and 114: emains as CachePending, there mustb
Page 115 and 116: M-engine Rules Msg from id Mstate A
Page 117 and 118: Chapter 6 The Migratory Cache Coher
Page 119 and 120: Commit/Reconcile Send Purge Loadl/C
Page 121 and 122: Mandatory Processor Rules Instructi
Page 123 and 124: while the memory sends a FlushReq m
Page 125 and 126: Lemma 38 D is strongly terminating
Page 127 and 128: Migratory Imperative Rule CRF Rules
Page 129 and 130: Cell(a,v,C[id ]) 2 Mem(s) _ Cell(a,
Page 131 and 132: According to Theorem-C and Lemma 45
Page 133 and 134: CacheReq message. In the latter cas
Page 135 and 136: Chapter 7 Cachet: A Seamless Integr
Page 137 and 138: 7.1.1 Putting Things Together It is
Page 139 and 140: Writeback Operations In Cachet, a w
Page 141 and 142: Composite Message Equivalent Sequen
Page 143 and 144: Imperative Processor Rules Instruct
Page 145 and 146: Invalid Commit/Reconcile Receive Ca
Page 147 and 148: Composite Imperative C-engine Rules
Page 149 and 150: 7.4 The Cachet Cache Coherence Prot
Page 151 and 152: Voluntary C-engine Rules Cstate Act
Page 153 and 154: The memory processes an incoming Ca
Page 155: The inaccuracy of memory states can
Page 159 and 160: Composite Mandatory Processor Rules
Page 161 and 162: memory regions simultaneously. In a
Page 163 and 164: Chapter 8 Conclusions This thesis h
Page 165 and 166: and heuristic policies. Mandatory r
Page 167 and 168: technique can be used to allow a ca
Page 169 and 170: Voluntary C-engine Rules Cstate Act
Page 171 and 172: FIFO Message Passing msg1 msg2 msg2
Page 173 and 174: [13] J. K. Archibald. The Cache Coh
Page 175 and 176: [41] A. Erlichson, N. Nuckolls, G.
Page 177 and 178: [71] J. Kuskin, D. Ofelt, M. Heinri
Page 179 and 180: [101] F. Pong and M. Dubois. A New
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