Design and Verification of Adaptive Cache Coherence Protocols ...

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CRF Rule Base Imperative Rules CRF-Loadl Loadl-on-Clean or Loadl-on-Dirty CRF-Storel Storel-on-Clean or Storel-on-Dirty CRF-Commit Commit-on-Clean or Commit-on-Invalid CRF-Reconcile Reconcile-on-Dirty or Reconcile-on-Invalid CRF-Cache C-Send-CacheReq + Message-Cache-to-Mem + M-Receive-CacheReq-&-Send-Cache + Message-Mem-to-Cache + C-Receive-Cache CRF-Writeback C-Send-Wb + Message-Cache-to-Mem + M-Receive-Wb-&-Send-WbAck + Message-Mem-to-Cache + C-Receive-WbAck CRF-Purge C-Purge 4.5.4 Soundness of Base Figure 4.8: Simulation of CRF in Base The simulation theorem demonstrates that each imperative rule of Base can be simulated by some CRF rules. Figure 4.7 shows that all the Base rules can be derived from the imperative rules (Base has no directive rule). Therefore, the Base protocol is a sound implementation of CRF. We mention in passing that each CRF rule can also be simulated by a sequence of Base rules. Given a CRF term s, we can lift it to a Base term by adding empty message queues and proper cache identi ers. For example, the cache operation in CRF can be simulated as follows: the cache issues a cache request, the network passes the request to the memory, the memory sends a cache message with the requested data, the network passes the cache message to the cache, and the cache receives the message and caches the data. Figure 4.8 gives the corresponding sequence of Base rules for the simulation of each CRF rule. 4.6 Liveness Proof of the Base Protocol In this section, we prove the liveness of Base by showing that each processor makes progress, that is, a memory instruction can always be completed eventually. We rst present some invariants that will be used in the liveness proof. 4.6.1 Some Invariants of Base Lemma 11 includes invariants regarding message generation and processing. Invariants (1)- (4) ensure that whenever a Loadl or Storel instruction is performed on an uncached address, the cache will send a CacheReq message to the memory whenever a Commit instruction is performed on a dirty cell, the cache will send a Wb message to the memory whenever a Reconcile instruction is performed on a clean cell, the cache will have the address purged. The proof simply follows the weak fairness of Rules P5, P10, P12 and P16. Invariants (5) and (6) ensure that whenever a cache receives a Cache or WbAck message, it will set the cache state to Clean. Invariants (7) and (8) ensure that whenever the memory 82
eceives a CacheReq message, it will send a Cache message to the cache whenever the memory receives a Wb message, it will send a WbAck message to the cache. These invariants can be proved based on the weak fairness of Rules MC1, MC2, MM1 and MM2. Invariants (9) and (10) ensure that each outgoing message will be delivered to its destina- tion's incoming queue. This can be proved based on the weak fairness of the message passing rules. Lemma 11 Given a Base sequence , (1) ht,Loadl(a)i2Pmb id( ) ^ a =2 Cache id( ) Msg(id ,H,CacheReq,a) 2 Cout id( ) (2) ht,Storel(a,-)i2Pmb id( ) ^ a =2 Cache id( ) Msg(id ,H,CacheReq,a) 2 Cout id( ) (3) ht,Commit(a)i2Pmb id ( ) ^ Cell(a,-,Dirty) 2 Cache id( ) Msg(id ,H,Wb,a,-) 2 Cout id ( ) (4) ht,Reconcile(a)i2Pmb id( ) ^ Cell(a,-,Clean) 2 Cache id( ) a =2 Cache id( ) (5) Msg(H,id ,Cache,a,-) 2 Cin id( ) Cell(a,-,Clean) 2 Cache id( ) (6) Msg(H,id ,WbAck,a) 2 Cin id ( ) Cell(a,-,Clean) 2 Cache id( ) (7) Msg(id ,H,CacheReq,a) 2 Min( ) Msg(H,id ,Cache,a,-) 2 Mout( ) (8) Msg(id ,H,Wb,a,-) 2 Min( ) Msg(H,id ,WbAck,a) 2 Mout( ) (9) msg 2 Cout id( ) ^ Dest(msg)=H msg 2 Min( ) (10) msg 2 Mout( ) ^ Dest(msg)=id msg 2 Cin id ( ) Lemma 12 ensures that if an address is cached in the CachePending or WbPending state, it will eventually be cached in the Clean state. Lemma 12 Given a Base sequence , (1) Cell(a,-,CachePending) 2 Cache id( ) Cell(a,-,Clean) 2 Cache id( ) (2) Cell(a,-,WbPending) 2 Cache id( ) Cell(a,-,Clean) 2 Cache id( ) Proof We rst show that if a cache sends a CacheReq or Wb message to the memory, the cache state will become Clean eventually. This can be represented by the following proposition the proof follows trivially from Lemma 11. Msg(id ,H,CacheReq,a) 2 Cout id( ) Cell(a,-,Clean) 2 Cache id( ) Msg(id ,H,Wb,a,-) 2 Cout id ( ) Cell(a,-,Clean) 2 Cache id( ) We then show that when a cache changes the state of a cache cell to CachePending or WbPend- ing, it sends a CacheReq or Wb message to the memory. The following proposition can be veri ed by simplychecking each Base rule. Cell(a,-,CachePending) =2 Cache id( ) ^ Cell(a,-,CachePending) 2 Cache id( ) ) Msg(id ,H,CacheReq,a) 2 Cout id ( ) Cell(a,-,WbPending) =2 Cache id( ) ^ Cell(a,-,WbPending) 2 Cache id( ) ) Msg(id ,H,Wb,a,-) 2 Cout id ( ) This completes the proof according to Theorem-A (see Section 2.5). 2 83
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CSAIL Computer Science and Artifici
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Design and Veri cation of Adaptive
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I am truly grateful to my parents f
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4 The Base Cache Coherence Protocol
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List of Figures 1.1 Impact of Archi
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Chapter 1 Introduction Shared memor
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transparent and exposed only for lo
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Example 1: Can both registers r1 an
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and release locks, which guard ever
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that are interconnected with an o -
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although various techniques have be
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y showing that each processor can a
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s1 if p (s1) ! s2 where s1 and s2 a
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Program counter (pc) +1 Instruction
Page 33 and 34: Branch target buffer (btb) Program
Page 35 and 36: instruction is waiting to be dispat
Page 37 and 38: Current State: Proc(ia, rf , rob, b
Page 39 and 40: Rule Name mem pmb mpb Next mem Next
Page 41 and 42: Specification Implementation t 1 B
Page 43 and 44: Intuitively, \2P " means that \P is
Page 45 and 46: (a) (b) PC 1005 PC 2000 Instruction
Page 47 and 48: ewritten to s2 according to rule R.
Page 49 and 50: It can be shown that the relaxed di
Page 51 and 52: Chapter 3 The Commit-Reconcile & Fe
Page 53 and 54: Producer Storel(a,v) Commit(a) Cons
Page 55 and 56: Commit/Reconcile Purge Loadl/Commit
Page 57 and 58: instructions, because of the lack o
Page 59 and 60: CRF-Relaxed-Commit Rule Site(sache,
Page 61 and 62: 3.4 Universality of the CRF Model M
Page 63 and 64: Translation from CRF to PSO: The Fe
Page 65 and 66: proc proc proc pmb mpb pmb mpb pmb
Page 67 and 68: Chapter 4 The Base Cache Coherence
Page 69 and 70: can be classi ed into two non-overl
Page 71 and 72: arbitrarily in an outgoing queue (t
Page 73 and 74: 4.3 The Imperative Rules of the Bas
Page 75 and 76: Imperative Processor Rules Instruct
Page 77 and 78: Figure 4.5 de nes the rules of the
Page 79 and 80: 4.5.2 Mapping from Base to CRF We d
Page 81 and 82: Base Imperative Rule CRF Rule IP1 (
Page 83: Base Rule Base Imperative Rule P1 I
Page 87 and 88: e completed if it has an in nite nu
Page 89 and 90: SYS Sys(MSITE, SITEs) System MSITE
Page 91 and 92: Commit/Reconcile C-Receive-WbAck Ru
Page 93 and 94: message can be resumed eventually.
Page 95 and 96: If the memory state shows that the
Page 97 and 98: 5.3.3 FIFO Message Passing The live
Page 99 and 100: Figure 5.7 gives the M-engine rules
Page 101 and 102: Backward-Message-Cache-to-Mem-for-W
Page 103 and 104: 5.4.3 Simulation of WP in CRF Theor
Page 105 and 106: WP Imperative Rule CRF Rules IP1 (L
Page 107 and 108: WP Rule WP Imperative & Directive R
Page 109 and 110: (4) Msg(H,id ,Cache,a,-)" 2 Cin id(
Page 111 and 112: This completes the proof according
Page 113 and 114: emains as CachePending, there mustb
Page 115 and 116: M-engine Rules Msg from id Mstate A
Page 117 and 118: Chapter 6 The Migratory Cache Coher
Page 119 and 120: Commit/Reconcile Send Purge Loadl/C
Page 121 and 122: Mandatory Processor Rules Instructi
Page 123 and 124: while the memory sends a FlushReq m
Page 125 and 126: Lemma 38 D is strongly terminating
Page 127 and 128: Migratory Imperative Rule CRF Rules
Page 129 and 130: Cell(a,v,C[id ]) 2 Mem(s) _ Cell(a,
Page 131 and 132: According to Theorem-C and Lemma 45
Page 133 and 134: CacheReq message. In the latter cas
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Chapter 7 Cachet: A Seamless Integr
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7.1.1 Putting Things Together It is
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Writeback Operations In Cachet, a w
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Composite Message Equivalent Sequen
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Imperative Processor Rules Instruct
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Invalid Commit/Reconcile Receive Ca
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Composite Imperative C-engine Rules
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7.4 The Cachet Cache Coherence Prot
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Voluntary C-engine Rules Cstate Act
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The memory processes an incoming Ca
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The inaccuracy of memory states can
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C-engine Rule of Cachet Deriving Im
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Composite Mandatory Processor Rules
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memory regions simultaneously. In a
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Chapter 8 Conclusions This thesis h
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and heuristic policies. Mandatory r
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technique can be used to allow a ca
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Voluntary C-engine Rules Cstate Act
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FIFO Message Passing msg1 msg2 msg2
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[13] J. K. Archibald. The Cache Coh
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[41] A. Erlichson, N. Nuckolls, G.
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[71] J. Kuskin, D. Ofelt, M. Heinri
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[101] F. Pong and M. Dubois. A New
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