Design and Verification of Adaptive Cache Coherence Protocols ...

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CRF model has both upward and downward compatibility, that is, the ability to run existing programs correctly and e ciently on a CRF machine, and the ability to run CRF programs well on existing machines. The CRF model was motivated from a directory-based cache coherence protocol that was originally designed for the MIT Start-Voyager multiprocessor system [11, 12]. The protocol veri cation requires a memory model that speci es the legal memory behaviors that the protocol was supposed to implement. Ironically, we did not have such a speci cation even after the protocol design was completed. As a result, it was not clear what invariants must be proved in order to ensure that the cache coherence protocol always exhibits the same behavior as sequential consistency for properly synchronized programs. The lack of a precise speci cation also made it di cult to understand and reason about the system behavior for programs that may have data races. To deal with this dilemma, we transformed the protocol by eliminating various directive operations and implementation details such as message queues, preserving the semantics throughout the transformation. This eventually led to CRF, an abstract protocol that cannot be further simpli ed. The CRF model can be implemented e ciently for shared memory systems, largely because the model itself is an abstraction of a highly optimized cache coherence protocol. We have designed a set of adaptive cache coherence protocols which are optimized for some common access patterns. The Base protocol is the most straightforward implementation of CRF, and is ideal for programs in which only necessary commit and reconcile operations are performed. The WP protocol allows a reconcile operation on a clean cache cell to complete without purging the cell so that the data can be accessed by subsequent load operations without causing a cache miss this is intended for programs that contain excessive reconcile operations. The Migratory protocol allows an address to be cachedinatmostonecache it ts well when one processor is likely to access an address many times before another processor accesses the same address. We further developed an adaptive cache coherence protocol called Cachet that provides a wide scope of adaptivity for DSM systems. The Cachet protocol is a seamless integration of multiple micro-protocols, and embodies both intra-protocol and inter-protocol adaptivity to achieve high performance under changing memory access patterns. A cache cell can be modi ed without the so-called exclusive ownership, which e ectively allows multiple writers for the same memory location simultaneously. This can reduce the average latency for write operations and alleviate potential cache thrashing due to false sharing. Moreover, the purge of an invalidated cache cell can be deferred to the next reconcile point, which can help reduce cache thrashing due to read-write false sharing. An early version of Cachet with only the Base and WP micro-protocols can be found elsewhere [113]. Since Cachet implements the CRF model, it is automatically a protocol that implements the memory models whose programs can be translated into CRF programs. Our view of adaptive protocols contains three layers: mandatory rules, voluntary rules 162
and heuristic policies. Mandatory rules are weakly or strongly fair to ensure the liveness of the system, while voluntary rules have no such requirement and are used to specify adaptive actions without giving particular enabling conditions. Therefore, we can also think of Cachet as a family of cache coherence protocols in that a heuristic policy for selecting adaptive operations de nes a complete protocol tailored for some particular access patterns. Di erent heuristic policies can exhibit di erent performance, but can never a ect the soundness and liveness of the protocol. We have proposed the two-stage Imperative-&-Directive methodology that separates the soundness and liveness concerns throughout protocol design and veri cation. The rst stage involves only imperative rules that specify coherence actions that determine the soundness of the system. The second stage involves directive rules and the integration of imperative and directive rules to ensure both the soundness and liveness simultaneously. The Imperative-&-Directive methodology can dramatically simplify the design and veri cation of sophisticated cache coherence protocols, because only imperative rules need to be considered while verifying soundness properties. This novel methodology was rst applied to the design of a cache coherence protocol for a DSM system with multi-level caches [110]. The following table illustrates the number of imperative and integrated rules for Cachet and its micro-protocols. As can be seen, although Cachet consists of about 150 rewriting rules, it has only 60 basic imperative rules that must be considered in the soundness proof, including many soundness-related invariants that are used in the liveness proof. Protocol Basic Rules Composite Rules Imperative Rules Integrated Rules Imperative Rules Integrated Rules Base 15 27 - - WP 19 45 - - Migratory 16 36 - - Cachet 60 113 15 33 We have shown that TRSs can be used to specify and verify computer architectures and dis- tributed protocols. While TRSs have something in common with some other formal techniques, we have found that the use of TRSs is more intuitive in both architecture descriptions and correctness proofs. The descriptions of micro-architectures and asynchronous protocols using TRSs are more precise than what one may nd in a modern textbook [55]. The \Architec- tures via TRSs" technique was rst applied to the speci cation and veri cation of a simple micro-architecture that employs register renaming and permits out-of-order instruction execu- tion [111]. TRSs can be used to prove the correctness of an implementation with respect to a speci- cation. The proof is based on simulation with respect to a mapping function. The mapping functions can be de ned based on the notion of drained terms, which can be obtained via forward or backward draining or a combination of both. The invariants often show up sys- tematically and can be veri ed by case analysis and simple induction. The promise of TRSs 163
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CSAIL Computer Science and Artifici
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Design and Veri cation of Adaptive
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I am truly grateful to my parents f
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4 The Base Cache Coherence Protocol
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List of Figures 1.1 Impact of Archi
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Chapter 1 Introduction Shared memor
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transparent and exposed only for lo
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Example 1: Can both registers r1 an
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and release locks, which guard ever
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that are interconnected with an o -
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although various techniques have be
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y showing that each processor can a
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s1 if p (s1) ! s2 where s1 and s2 a
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Program counter (pc) +1 Instruction
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Branch target buffer (btb) Program
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instruction is waiting to be dispat
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Current State: Proc(ia, rf , rob, b
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Rule Name mem pmb mpb Next mem Next
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Specification Implementation t 1 B
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Intuitively, \2P " means that \P is
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(a) (b) PC 1005 PC 2000 Instruction
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ewritten to s2 according to rule R.
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It can be shown that the relaxed di
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Chapter 3 The Commit-Reconcile & Fe
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Producer Storel(a,v) Commit(a) Cons
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Commit/Reconcile Purge Loadl/Commit
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instructions, because of the lack o
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CRF-Relaxed-Commit Rule Site(sache,
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3.4 Universality of the CRF Model M
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Translation from CRF to PSO: The Fe
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proc proc proc pmb mpb pmb mpb pmb
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Chapter 4 The Base Cache Coherence
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can be classi ed into two non-overl
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arbitrarily in an outgoing queue (t
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4.3 The Imperative Rules of the Bas
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Imperative Processor Rules Instruct
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Figure 4.5 de nes the rules of the
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4.5.2 Mapping from Base to CRF We d
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Base Imperative Rule CRF Rule IP1 (
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Base Rule Base Imperative Rule P1 I
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eceives a CacheReq message, it will
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e completed if it has an in nite nu
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SYS Sys(MSITE, SITEs) System MSITE
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Commit/Reconcile C-Receive-WbAck Ru
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message can be resumed eventually.
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If the memory state shows that the
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5.3.3 FIFO Message Passing The live
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Figure 5.7 gives the M-engine rules
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Backward-Message-Cache-to-Mem-for-W
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5.4.3 Simulation of WP in CRF Theor
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WP Imperative Rule CRF Rules IP1 (L
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WP Rule WP Imperative & Directive R
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(4) Msg(H,id ,Cache,a,-)" 2 Cin id(
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This completes the proof according
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Page 115 and 116: M-engine Rules Msg from id Mstate A
Page 117 and 118: Chapter 6 The Migratory Cache Coher
Page 119 and 120: Commit/Reconcile Send Purge Loadl/C
Page 121 and 122: Mandatory Processor Rules Instructi
Page 123 and 124: while the memory sends a FlushReq m
Page 125 and 126: Lemma 38 D is strongly terminating
Page 127 and 128: Migratory Imperative Rule CRF Rules
Page 129 and 130: Cell(a,v,C[id ]) 2 Mem(s) _ Cell(a,
Page 131 and 132: According to Theorem-C and Lemma 45
Page 133 and 134: CacheReq message. In the latter cas
Page 135 and 136: Chapter 7 Cachet: A Seamless Integr
Page 137 and 138: 7.1.1 Putting Things Together It is
Page 139 and 140: Writeback Operations In Cachet, a w
Page 141 and 142: Composite Message Equivalent Sequen
Page 143 and 144: Imperative Processor Rules Instruct
Page 145 and 146: Invalid Commit/Reconcile Receive Ca
Page 147 and 148: Composite Imperative C-engine Rules
Page 149 and 150: 7.4 The Cachet Cache Coherence Prot
Page 151 and 152: Voluntary C-engine Rules Cstate Act
Page 153 and 154: The memory processes an incoming Ca
Page 155 and 156: The inaccuracy of memory states can
Page 157 and 158: C-engine Rule of Cachet Deriving Im
Page 159 and 160: Composite Mandatory Processor Rules
Page 161 and 162: memory regions simultaneously. In a
Page 163: Chapter 8 Conclusions This thesis h
Page 167 and 168: technique can be used to allow a ca
Page 169 and 170: Voluntary C-engine Rules Cstate Act
Page 171 and 172: FIFO Message Passing msg1 msg2 msg2
Page 173 and 174: [13] J. K. Archibald. The Cache Coh
Page 175 and 176: [41] A. Erlichson, N. Nuckolls, G.
Page 177 and 178: [71] J. Kuskin, D. Ofelt, M. Heinri
Page 179 and 180: [101] F. Pong and M. Dubois. A New
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