Design and Verification of Adaptive Cache Coherence Protocols ...

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Lemma 34 Given a WP sequence , (1) Loadl(a) 2 Pmb id( ) Loadl(a) 2 Pmb id( ) ^ (Cell(a,-,Clean) 2 Cache id( ) _ Cell(a,-,Dirty) 2 Cache id( )) (2) Storel(a,-) 2 Pmb id( ) Storel(a,-) 2 Pmb id( ) ^ (Cell(a,-,Clean) 2 Cache id( ) _ Cell(a,-,Dirty) 2 Cache id( )) (3) Commit(a) 2 Pmb id( ) Commit(a) 2 Pmb id ( ) ^ (Cell(a,-,Clean) 2 Cache id( ) _ a =2 Cache id( )) (4) Reconcile(a) 2 Pmb id( ) Reconcile(a) 2 Pmb id( ) ^ (Cell(a,-,Clean) 2 Cache id( ) _ Cell(a,-,Dirty) 2 Cache id( ) _ a =2 Cache id( )) Proof We rst show that when a processor intends to execute an instruction, the cache cell will be set to an appropriate state. This can be represented by the following proposition the proof follows from Lemmas 27, 32 and 33. Loadl(a) 2 Pmb id( ) Cell(a,-,Clean) 2 Cache id( ) _ Cell(a,-,Dirty) 2 Cache id( ) Storel(a,-) 2 Pmb id( ) Cell(a,-,Clean) 2 Cache id( ) _ Cell(a,-,Dirty) 2 Cache id( ) Commit(a) 2 Pmb id ( ) Cell(a,-,Clean) 2 Cache id( ) _ a =2 Cache id( ) Reconcile(a) 2 Pmb id( ) Cell(a,-,Clean) 2 Cache id( ) _ Cell(a,-,Dirty) 2 Cache id( ) _ a =2 Cache id( ) We then show that an instruction can be completed only when the address is cached in an appropriate state. This can be represented by the following proposition, which can be veri ed by simplychecking the WP rules that allow an instruction to be retired. ht,Loadl(a)i2Pmb id( ) ^ ht,Loadl(a)i =2 Pmb id( ) ) Cell(a,-,Clean) 2 Cache id( ) _ Cell(a,-,Dirty) 2 Cache id( ) ht,Storel(a,-)i2Pmb id( ) ^ ht,Storel(a,-)i =2 Pmb id( ) ) Cell(a,-,Clean) 2 Cache id( ) _ Cell(a,-,Dirty) 2 Cache id( ) ht,Commit(a)i2Pmb id ( ) ^ ht,Commit(a)i =2 Pmb id( ) ) Cell(a,-,Clean) 2 Cache id( ) _ a =2 Cache id( ) ht,Reconcile(a)i2Pmb id( ) ^ ht,Reconcile(a)i =2 Pmb id( ) ) Cell(a,-,Clean) 2 Cache id( ) _ Cell(a,-,Dirty) 2 Cache id( ) _ a =2 Cache id( ) This completes the proof according to Theorem-B. 2 The liveness of WP ensures that a memory instruction can always be completed eventually. This is described by the following theorem, which trivially follows from Lemma 34. Note that Rules P1, P2, P6, P7, P11, P15, P16, P17 and P20 are strongly fair. Theorem 35 (Liveness of WP) Given a WP sequence , (1) ht,Loadl(-)i2Pmb id( ) ht,-i2Mpb id ( ) (2) ht,Storel(-,-)i2Pmb id( ) ht,Acki2Mpb id ( ) (3) ht,Commit(-)i2Pmb id( ) ht,Acki2Mpb id ( ) (4) ht,Reconcile(-)i2Pmb id( ) ht,Acki2Mpb id ( ) 112
M-engine Rules Msg from id Mstate Action Next Mstate hCacheReq,ai Cell(a,v,C[dir,hint]) (id =2 dir) hCache,a,vi!id Cell(a,v,C[id jdir,hint]) SF Cell(a,v,C[dir,hint]) (id 2 dir) Cell(a,v,C[dir,hint]) Cell(a,v,T[dir,sm,hint]) (id =2 dir) stall message Cell(a,v,T[dir,sm,hint]) Cell(a,v,T[dir,sm,hint]) (id 2 dir) Cell(a,v,T[dir,sm,hint]) hWb,a,vi Cell(a,v1,C[id jdir,hint]) hPurgeReq,ai!dir Cell(a,v1,T[dir,(id ,v),hint]) Cell(a,v1,T[id jdir,sm,hint]) Cell(a,v1,T[dir,(id ,v)jsm,hint]) hPurge,ai Cell(a,v,C[id jdir,hint]) Cell(a,v,C[dir,hint]) Cell(a,v,T[id jdir,sm,hint]) Cell(a,v,T[dir,sm,id jhint]) Cell(a,-,T[ ,(id ,v)jsm,hint]) hFlushAck,ai!id Cell(a,v,T[ ,sm,id jhint]) Cell(a,-,T[ ,(id ,v),hint]) hWbAck,ai!id Cell(a,v,C[id ,hint]) Cell(a,v,T[ , ,hint]) Cell(a,v,C[ ,hint]) Cell(a,v,C[dir,id jhint]) (id =2 dir) hCache,a,vi!id Cell(a,v,C[id jdir,hint]) Cell(a,v,C[dir,id jhint]) Cell(a,v,C[dir,hint]) Cell(a,v,T[dir,sm,id jhint]) Cell(a,v,T[dir,sm,hint]) Figure 5.10: Memory Engine Rules of an Update Protocol 5.6 An Update Protocol from WP The WP protocol contains voluntary rules that can be invoked under various heuristic policies. Di erent heuristic policies can lead to di erent performance, but the soundness and liveness of the system are always guaranteed. To build a concrete adaptive protocol one has to decide only on the conditions in which eachvoluntary rule should be applied. This policy decision is taken on the basis of an expected or observed behavior of the program. To demonstrate the use of voluntary rules, we build an update protocol from WP. The memory maintains some hueristic information about the cache sites that may need to be updated. It behaves as a hint for the invocation of the voluntary rule that sends a data copy to a cache site even though no cache request is received. The heuristic information is called soft state since it has no impact on the soundness and liveness of the protocol. Figure 5.10 gives the M-engine rules for the update protocol (the processor and C-engine rules remain unchanged). When the memory receives a purge acknowledgment, it records the cache identi er as a hint for future cache update. Later when the memory is updated, it can send a data copy to the cache site in which the address was just purged. Note that a cache identi er in the heuristic information can be removed at any time without taking any action. The correctness of the update protocol follows from two observations. First, with all the heuristic information removed, each rule of the update protocol can be projected to either a mandatory or voluntary rule of WP, or a rule that takes no action (that is, the rule has identical left-hand-side and right-hand-side). This guarantees the soundness of the protocol. Second, the action of each mandatory rule of WP can be invoked under the same condition in the update protocol, that is, its applicability isnotcontingent uponany heuristic information. This guarantees the liveness of the protocol. 113
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CSAIL Computer Science and Artifici
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Design and Veri cation of Adaptive
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I am truly grateful to my parents f
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4 The Base Cache Coherence Protocol
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List of Figures 1.1 Impact of Archi
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Chapter 1 Introduction Shared memor
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transparent and exposed only for lo
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Example 1: Can both registers r1 an
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and release locks, which guard ever
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that are interconnected with an o -
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although various techniques have be
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y showing that each processor can a
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s1 if p (s1) ! s2 where s1 and s2 a
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Program counter (pc) +1 Instruction
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Branch target buffer (btb) Program
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instruction is waiting to be dispat
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Current State: Proc(ia, rf , rob, b
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Rule Name mem pmb mpb Next mem Next
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Specification Implementation t 1 B
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Intuitively, \2P " means that \P is
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(a) (b) PC 1005 PC 2000 Instruction
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ewritten to s2 according to rule R.
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It can be shown that the relaxed di
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Chapter 3 The Commit-Reconcile & Fe
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Producer Storel(a,v) Commit(a) Cons
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Commit/Reconcile Purge Loadl/Commit
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instructions, because of the lack o
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CRF-Relaxed-Commit Rule Site(sache,
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3.4 Universality of the CRF Model M
Page 63 and 64: Translation from CRF to PSO: The Fe
Page 65 and 66: proc proc proc pmb mpb pmb mpb pmb
Page 67 and 68: Chapter 4 The Base Cache Coherence
Page 69 and 70: can be classi ed into two non-overl
Page 71 and 72: arbitrarily in an outgoing queue (t
Page 73 and 74: 4.3 The Imperative Rules of the Bas
Page 75 and 76: Imperative Processor Rules Instruct
Page 77 and 78: Figure 4.5 de nes the rules of the
Page 79 and 80: 4.5.2 Mapping from Base to CRF We d
Page 81 and 82: Base Imperative Rule CRF Rule IP1 (
Page 83 and 84: Base Rule Base Imperative Rule P1 I
Page 85 and 86: eceives a CacheReq message, it will
Page 87 and 88: e completed if it has an in nite nu
Page 89 and 90: SYS Sys(MSITE, SITEs) System MSITE
Page 91 and 92: Commit/Reconcile C-Receive-WbAck Ru
Page 93 and 94: message can be resumed eventually.
Page 95 and 96: If the memory state shows that the
Page 97 and 98: 5.3.3 FIFO Message Passing The live
Page 99 and 100: Figure 5.7 gives the M-engine rules
Page 101 and 102: Backward-Message-Cache-to-Mem-for-W
Page 103 and 104: 5.4.3 Simulation of WP in CRF Theor
Page 105 and 106: WP Imperative Rule CRF Rules IP1 (L
Page 107 and 108: WP Rule WP Imperative & Directive R
Page 109 and 110: (4) Msg(H,id ,Cache,a,-)" 2 Cin id(
Page 111 and 112: This completes the proof according
Page 113: emains as CachePending, there mustb
Page 117 and 118: Chapter 6 The Migratory Cache Coher
Page 119 and 120: Commit/Reconcile Send Purge Loadl/C
Page 121 and 122: Mandatory Processor Rules Instructi
Page 123 and 124: while the memory sends a FlushReq m
Page 125 and 126: Lemma 38 D is strongly terminating
Page 127 and 128: Migratory Imperative Rule CRF Rules
Page 129 and 130: Cell(a,v,C[id ]) 2 Mem(s) _ Cell(a,
Page 131 and 132: According to Theorem-C and Lemma 45
Page 133 and 134: CacheReq message. In the latter cas
Page 135 and 136: Chapter 7 Cachet: A Seamless Integr
Page 137 and 138: 7.1.1 Putting Things Together It is
Page 139 and 140: Writeback Operations In Cachet, a w
Page 141 and 142: Composite Message Equivalent Sequen
Page 143 and 144: Imperative Processor Rules Instruct
Page 145 and 146: Invalid Commit/Reconcile Receive Ca
Page 147 and 148: Composite Imperative C-engine Rules
Page 149 and 150: 7.4 The Cachet Cache Coherence Prot
Page 151 and 152: Voluntary C-engine Rules Cstate Act
Page 153 and 154: The memory processes an incoming Ca
Page 155 and 156: The inaccuracy of memory states can
Page 157 and 158: C-engine Rule of Cachet Deriving Im
Page 159 and 160: Composite Mandatory Processor Rules
Page 161 and 162: memory regions simultaneously. In a
Page 163 and 164: Chapter 8 Conclusions This thesis h
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and heuristic policies. Mandatory r
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technique can be used to allow a ca
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Voluntary C-engine Rules Cstate Act
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FIFO Message Passing msg1 msg2 msg2
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[13] J. K. Archibald. The Cache Coh
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[41] A. Erlichson, N. Nuckolls, G.
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[71] J. Kuskin, D. Ofelt, M. Heinri
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[101] F. Pong and M. Dubois. A New
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