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Design and Verification of Adaptive Cache Coherence Protocols ...

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7.1.1 Putting Things Together<br />

It is easy to see that di erent addresses can employ di erent micro-protocols without any in-<br />

terference. The primary objective <strong>of</strong> <strong>Cache</strong>t is to integrate the micro-protocols in a seamless<br />

fashion in that di erent caches can use di erent micro-protocols on the same address simulta-<br />

neously, <strong>and</strong> a cache can dynamically switch from one micro-protocol to another. For example,<br />

when something is known about the access pattern for a speci c memory region, a cache can<br />

employ an appropriate micro-protocol for that region.<br />

Di erent micro-protocols have di erent implications on the execution <strong>of</strong> memory instruc-<br />

tions. The micro-protocols form an access privilege hierarchy. The Migratory protocol has the<br />

most privilege in that both commit <strong>and</strong> reconcile operations have no impact on the cache cell,<br />

while the Base protocol has the least privilege in that both commit <strong>and</strong> reconcile operations<br />

may require proper actions to be taken on the cache cell. The WP protocol has less privilege<br />

than Migratory but more privilege than Base. It allows reconcile operations to complete in the<br />

presence <strong>of</strong> a clean copy, but requires a dirty copy to be written back before commit operations<br />

on that address can complete.<br />

With appropriate h<strong>and</strong>ling, the Base protocol can coexist with either WP or Migratory on<br />

the same address. The Base protocol requires that a dirty be written back to the memory on a<br />

commit, <strong>and</strong> a clean copy be purged on a reconcile so that the subsequent load operation must<br />

retrieve the data from the memory. This gives the memory an opportunity totake appropriate<br />

actions whenever necessary, regardless <strong>of</strong> how the address is cached in other caches at the time.<br />

In contrast, WP <strong>and</strong> Migratory cannot coexist with each other on the same address.<br />

Since di erent micro-protocols have di erent treatment for Commit <strong>and</strong> Reconcile instruc-<br />

tions, a cache must be able to tell which micro-protocol is in use for each cache cell. We can<br />

annotate a cache state with a subscript to represent the operational micro-protocol: Cleanb<br />

<strong>and</strong> Dirtyb are Base states, Cleanw <strong>and</strong> Dirtyw are WP states, <strong>and</strong> Cleanm <strong>and</strong> Dirtym are<br />

Migratory states. The <strong>Cache</strong>t protocol draws no distinction between di erent micro-protocols<br />

for an uncached address, or an address cached in a transient state. We can also use subscripts<br />

to distinguish protocol messages whenever necessary. For example, the memory can supply a<br />

Base, WP or Migratory copy to a cache via a <strong>Cache</strong>b, <strong>Cache</strong>w or <strong>Cache</strong>m message. A cache<br />

can write a dirty copy back to the memory via a Wbb or Wbw message, depending on whether<br />

Base or WP is in use on the address.<br />

7.1.2 Dynamic Micro-protocol Switch<br />

The <strong>Cache</strong>t protocol provides inter-protocol adaptivity viadowngrade <strong>and</strong> upgrade operations.<br />

A downgrade operation switches a cache cell to a less privileged micro-protocol, while an up-<br />

grade operation switches a cache cell to a more privileged micro-protocol. Figure 7.2 shows<br />

the cache state transitions caused by downgrade <strong>and</strong> upgrade operations (associated with each<br />

transition is the corresponding protocol message that is generated or received at the cache site).<br />

135

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