Design and Verification of Adaptive Cache Coherence Protocols ...

I2 ) Loadl Storel Fencerr Fencerw Fencewr Fenceww Commit Reconcile
I1 + (a 0 ) (a 0 ,v 0 ) (a 0 1,a 0 2) (a 0 1,a 0 2) (a 0 1,a 0 2) (a 0 1,a 0 2) (a 0 ) (a 0 )
Loadl(a) true a 6= a 0
a 6= a 0 1 a 6= a 0 Storel(a,v) a 6= a
1 true true true true
0
a 6= a 0 true true true true a 6= a 0 true
Fencerr(a1,a2) true true true true true true true a2 6= a 0
Fencerw(a1,a2) true a2 6= a 0
true true true true true true
Fencewr(a1,a2) true true true true true true true a2 6= a 0
Fenceww(a1,a2) true a2 6= a 0
true true true true true true
Commit(a) true true true true a 6= a 0 1 a 6= a 0 1 true true
Reconcile(a) a 6= a 0 true true true true true true true
Figure 3.6: Instruction Reordering Table of CRF
imposes ordering constraints on preceding Commit instructions instead of Storel instructions,
since only a Commit can force the dirty copy to be written back to the memory. It makes little
sense to ensure a Storel is completed if it is not followed by a Commit. Likewise, a Fence r
instruction imposes ordering constraints on following Reconcile instructions instead of Loadl
instructions, since only a Reconcile can force a stale copy tobepurged.It makes little sense to
postpone a Loadl if it is not preceded by a Reconcile.
Figure 3.6 concisely de nes the conditions under which two adjacent CRF instructions can
be reordered (assume instruction I1 precedes instruction I2, and a `true' condition indicates that
the reordering is allowed). The underlying rationale is to allow maximum reordering exibility
for out-of-order execution. There are 64 reordering rules de ned by the reordering table. As
an example, the rule corresponding to the Storel-Storel entry allows two Storel instructions to
be reordered if they access di erent addresses:
CRF-Reorder-Storel-Storel Rule
ht,Storel(a,v)iht 0 ,Storel(a 0 ,v 0 )i if a 6= a 0
! ht 0 ,Storel(a 0 ,v 0 )iht,Storel(a,v)i
This rule is commutative in the sense that reordered instructions can be reordered back.
However, not all the reordering rules commute. For example, the rule represented by the Fencerr-
Loadl entry does not commute: once the reordering is performed, the instructions cannot be
reordered back unless the address of the Loadl instruction and the pre-address of the Fencerr
instruction are di erent (according to the Loadl-Fencerr entry).
We also need a rule to discharge a memory fence:
CRF-Fence Rule
Site(sache, ht,Fence (a1,a2)ipmb, mpb, proc)
! Site(sache, pmb, mpbjht,Acki, proc)
It is worth pointing out that appropriate extension is needed for CRF in order to de ne the
semantics of synchronization instructions such as Test-&-Set, Swap, Lock/Unlock and Load-
&-Reserve/Store-Conditional. The CRF model by itself contains no particular synchronization
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