Design and Verification of Adaptive Cache Coherence Protocols ...

Design and Veri cation of Adaptive Cache Coherence Protocols
Abstract
by
Xiaowei Shen
Submitted to the Department of Electrical Engineering and Computer Science
on January 5, 2000
in partial ful llment of the requirements for the degree of
Doctor of Philosophy
We propose to apply Term Rewriting Systems (TRSs) to modeling computer architectures and
distributed protocols. TRSs o er a convenient way to precisely describe asynchronous systems
and can be used to verify the correctness of an implementation with respect to a speci cation.
This dissertation illustrates the use of TRSs by giving the operational semantics of a simple
instruction set, and a processor that implements the same instruction set on a micro-architecture
that allows register renaming and speculative execution.
A mechanism-oriented memory model called Commit-Reconcile & Fences (CRF) is presented
that allows scalable implementations of shared memory systems. The CRF model exposes a
semantic notion of caches, referred to as saches, and decomposes memory access operations
into simpler instructions. In CRF, a memory load operation becomes a Reconcile followed by a
Loadl, and a memory store operation becomes a Storel followed by a Commit. The CRF model
can serve as a stable interface between computer architects and compiler writers.
We design a family of cache coherence protocols for distributed shared memory systems. Each
protocol is optimized for some speci c access patterns, and contains a set of voluntary rules to
provide adaptivity that can be invoked whenever necessary. It is proved that each protocol is a
correct implementation of CRF, and thus a correct implementation of any memory model whose
programs can be translated into CRF programs. To simplify protocol design and veri cation,
we employ anovel two-stage design methodology called Imperative-&-Directive that addresses
the soundness and liveness concerns separately throughout protocol development.
Furthermore, an adaptive cache coherence protocol called Cachet is developed that provides
enormous adaptivity for programs with di erent access patterns. The Cachet protocol is a
seamless integration of multiple micro-protocols, and embodies both intra-protocol and interprotocol
adaptivity that can be exploited via appropriate heuristic mechanisms to achieve optimal
performance under changing program behaviors. The Cachet protocol allows store accesses
to be performed without the exclusive ownership, which can notably reduce store latency and
alleviate cache thrashing due to false sharing.
Thesis Supervisor: Arvind
Title: Professor of Electrical Engineering and Computer Science
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