M-engine Rule <strong>of</strong> <strong>Cache</strong>t Deriving Imperative & Directive Rules VM1 IM1 VM2 IM2 VM3 Send-DownReqwb VM4 Send-DownReqmw VM5 Send-DownReqwb MM1 IM3 MM2 MM3 IM4 MM4 IM4 MM5 Send-DownReqmw MM6 MM7 MM8 IM5 MM9 IM5 MM10 IM5 MM11 IM6 + Send-DownReqwb MM12 IM6 MM13 IM7 + Send-DownReqwb MM14 IM7 MM15 IM8 + Send-DownReqmw + Send-DownReqwb MM16 IM8 + Send-DownReqwb MM17 IM8 MM18 IM9 MM19 IM9 MM20 IM9 MM21 IM10 MM22 IM10 MM23 IM11 MM24 IM11 MM25 IM11 MM26 IM12 MM27 IM12 MM28 IM12 MM29 IM13 MM30 IM13 MM31 IM13 MM32 IM14 MM33 IM15 MM34 Figure 7.16: Derivation <strong>of</strong> Memory Engine Rules <strong>of</strong> <strong>Cache</strong>t Figure 7.18 gives the basic rules used in the simulation <strong>of</strong> each composite rule. The <strong>Cache</strong>t Protocol Appendix A gives the speci cation <strong>of</strong> the complete <strong>Cache</strong>t protocol, which contains the basic rules de ned in Figures 7.11, 7.12 <strong>and</strong> 7.13, <strong>and</strong> the composite rules de ned in Figure 7.17. The <strong>Cache</strong>t protocol is an adaptive cache coherence protocol, although for pedagogic reason it has been been presented as an integration <strong>of</strong> several micro-protocols. One can also think <strong>Cache</strong>t as a family <strong>of</strong> protocols because <strong>of</strong> the presence <strong>of</strong> voluntary rules that can be invoked without the execution <strong>of</strong> an instruction or the receipt <strong>of</strong> a message. The existence <strong>of</strong> voluntary rules provides enormous extensibility in the sense that various heuristic messages <strong>and</strong> states can be employed to invoke these rules. As an example <strong>of</strong> how the adaptivity can be exploited, consider a DSM system with limited directory space. When the memory receives a cache request, it can respond under Base or WP. 156
Composite M<strong>and</strong>atory Processor Rules Instruction Cstate Action Next Cstate Commit(a) Cell(a,v,Dirtyw) stall, hWbw,a,vi!H Cell(a,v,WbPending) CP1 Composite Voluntary C-engine Rules Cstate Action Next Cstate Cell(a,v,Dirtyw) hWbw,a,vi!H Cell(a,v,WbPending) CVC1 Cell(a,v,Cleanm) hDownmb,ai!H Cell(a,v,Cleanb) CVC2 Cell(a,v,Dirtym) hDownVmb,a,vi!H Cell(a,v,Cleanb) CVC3 Composite M<strong>and</strong>atory C-engine Rules h<strong>Cache</strong>m,a,vi Cell(a,-,Cleanb) Cell(a,v,Cleanm) CMC1 Cell(a,v1,Dirtyb) Cell(a,v1,Dirtym) CMC2 Cell(a,v1,WbPending) Cell(a,v1,WbPending) CMC3 Cell(a,-,<strong>Cache</strong>Pending) Cell(a,v,Cleanm) CMC4 a =2 cache Cell(a,v,Cleanm) CMC5 hWbAckm,ai Cell(a,v,WbPending) Cell(a,v,Cleanm) CMC6 hDownReqmb,ai Cell(a,v,Cleanb) Cell(a,v,Cleanb) CMC7 Cell(a,v,Dirtyb) Cell(a,v,Dirtyb) CMC8 Cell(a,v,Cleanw) hDownwb,ai!H Cell(a,v,Cleanb) CMC9 Cell(a,v,Dirtyw) hDownwb,ai!H Cell(a,v,Dirtyb) CMC10 Cell(a,v,Cleanm) hDownmb,ai!H Cell(a,v,Cleanb) CMC11 Cell(a,v,Dirtym) hDownVmb,a,vi!H Cell(a,v,Cleanb) CMC12 Cell(a,v,WbPending) Cell(a,v,WbPending) CMC13 Cell(a,-,<strong>Cache</strong>Pending) Cell(a,-,<strong>Cache</strong>Pending) CMC14 a =2 cache a =2 cache CMC15 Composite Voluntary M-engine Rules Mstate Action Next Mstate Cell(a,v,Cw[ ]) h<strong>Cache</strong>m,a,vi!id Cell(a,v,Cm[id ]) CVM1 Cell(a,v,Cm[id ]) hDownReqmb,ai!id Cell(a,v,Tm[id , ]) CVM2 Composite M<strong>and</strong>atory M-engine Rules hWbw,a,vi Cell(a,v1,Cw[id jdir]) hDownReqwb,ai!dir Cell(a,v1,Tw[dir,(id ,v)]) CMM1 Cell(a,v1,Tw[id jdir,sm]) Cell(a,v1,Tw[dir,(id ,v)jsm]) CMM2 Cell(a,v1,Cm[id ]) Cell(a,v1,Tw[ ,(id ,v)]) CMM3 Cell(a,v1,T 0 m[id ]) Cell(a,v1,Tw[ ,(id ,v)]) CMM4 Cell(a,v1,Tm[id ,sm]) Cell(a,v1,Tw[ ,(id ,v)jsm]) CMM5 hDownmb,ai Cell(a,v,Cm[id ]) Cell(a,v,Cw[ ]) CMM6 Cell(a,v,T 0 m[id ]) Cell(a,v,Cw[ ]) CMM7 Cell(a,v,Tm[id ,sm]) Cell(a,v,Tw[ ,sm]) CMM8 hDownVmb,a,vi Cell(a,-,Cm[id ]) Cell(a,v,Cw[ ]) CMM9 Cell(a,-,T 0 m[id ]) Cell(a,v,Cw[ ]) CMM10 Cell(a,-,Tm[id ,sm]) Cell(a,v,Tw[ ,sm]) CMM11 Cell(a,-,Tw[ ,(id ,v)]) hWbAckm,ai!id Cell(a,v,Cm[id ]) CMM12 Figure 7.17: Composite Rules <strong>of</strong> <strong>Cache</strong>t 157
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CSAIL Computer Science and Artifici
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Design and Veri cation of Adaptive
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I am truly grateful to my parents f
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4 The Base Cache Coherence Protocol
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List of Figures 1.1 Impact of Archi
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Chapter 1 Introduction Shared memor
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transparent and exposed only for lo
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Program counter (pc) +1 Instruction
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Branch target buffer (btb) Program
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instruction is waiting to be dispat
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Rule Name mem pmb mpb Next mem Next
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Specification Implementation t 1 B
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It can be shown that the relaxed di
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3.4 Universality of the CRF Model M
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Figure 5.7 gives the M-engine rules
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Backward-Message-Cache-to-Mem-for-W
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