Superconducting Technology Assessment - nitrd

Parameter spreads in superconductive circuits can cause either hard failures or soft failures. Extensive data for important
circuit elements such as junctions, resistors, and inductors in a present day superconductive process indicates ~1 - 4%
spreads (1σ) for local variations (on-chip), 5% for global variation (across-wafer) and 10% for run-to-run reproducibility.
The most critical circuit element is the JJ. Table 4-8 shows on-chip I c spreads for several Nb IC generations at NGST.
(Note that the 2004 column reports early results for a new process that was far from optimized.)
Junction scaling is necessary to achieve higher clock speeds. It is estimated that 0.5 - 0.8 µm junctions will be
required to meet the 50 - 100 GHz clock requirement. Unlike transistors, for which the gate length is the critical
dimension (CD) and the circuit is not as sensitive to local variations in gate length, tight areal CD control is required
for JJs, since critical current (which scales with junction area) is the important parameter. As feature sizes decrease,
absolute CD control will need to improve proportionately. Although the preliminary 2004 result in Table 4-8,
obtained at NGST in collaboration with JPL, is promising in that regard, there are few data available on submicron
JJ circuits. However, additional data are available for magnetic random access memory (MRAM) technology, which
is also based on tunnel junctions with Al oxide barriers, the same barrier used in Nb JJs. IBM has demonstrated a
16 Mb MRAM chip based on deep-sub-µm (0.14 µm 2 ) tunnel junctions which exhibit resistance spreads of ~2%
(1σ). This indicates that 2% J c control in JJs of similar size is possible.
Local spreads are the most important in determining circuit size, while global and run-to-run variations limit yield
(i.e., the number of good chips). Present day spreads are consistent with circuit densities of 1M JJ/cm 2 , even while
taking the low bit-error-rate (BER) requirement of general computing into account (but excluding other yield-limiting
effects such as defect density). However, present day tools and methods may not be adequate, and the ability to
control CD variation could limit progress towards integration levels beyond 1M JJ/cm 2 . Commercially available
lithography tools provide resolution control of 0.03 µm (2σ) for a feature size of 0.65 µm. For 0.8 µm junctions,
this translates to ±5% I c spread (1σ) for two neighboring junctions, for just the exposure portion of the process.
The final CD is a result of several other processes including developing and etching, each of which has a CD tolerance.
A net CD tolerance of ±5% may limit yield of large circuits. This suggests that other methods or more advanced
tools may be needed.
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TABLE 4-8. JUNCTION CRITICAL CURRENT VARIATION
Year 1998 2000 2002 2004
Junction size (µm) 2.5 1.75 1.25 0.80
Junction current density (kA/cm 2 ) 2 4 8 20
∆I c (1σ) % ±1.1
∆I c (max-min) % ±2.5
±1.4 ±1.4 ±2.30
±3.4 ±3.5 ±5.9
Understanding and predicting yield will be important
because it will have a strong bearing on sizing the resources
needed to produce a petaflops-scale computer.